Electronic – What are these gaps in PCB polygon pours near vias of the same net

altiumcopper-pourpcb-designvia

When adding polygon pours to a power layer on my PCB in Altium Designer (v17), I'm getting weird clearance gaps near vias. The poly and vias are connected to the same net. I'm new to Altium, so I'm not sure what's causing this.

Gaps in polygon pour in Altium Designer

  • I've checked Design Rules > Polygon Connect and tried both Direct and Relief connect (no change). I don't think it's a relief because if it was it would encircle the via.
  • On the polygon properties, I have tried turning on/off Remove Dead Copper, Remove Islands by Area, and Remove Narrow Necks, but the gaps persist (albeit with some corner sharpness differences).

I put some vias near the edge of the poly to try and figure this out:

Gaps in polygon pour in Altium Designer, near edge

I suspect there may be a design rule affecting it, but I am not sure what to look for.

What should I check in Altium that controls gaps around/near vias on polygon pours of the same net?

Best Answer

Go to Design -> Rules, look for a Polygon Connect Rule (NOT a Plane connect rule).

In that rule, make sure that "Direct Connect" is selected. Confirm, then leave that dialog. Repour all polygons (T->G->A). Now, check if you can still see those holes.

I have a feeling that these come from a thermal relief connect (which is setup in said rule), overlapped by tracks.