drammemory
I have read a paper about the cold-boot attack led by J. Alex Halderman.
Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf
The paper shows the decay of a data in memory without power. They used this picture as example:
Obviously, the discharged state for some capacitors are represented as 1(white) others as 0(black).
What is the reason for this? Why not represent every discharged capacitor as 0? Can you give me some insight in this topic, or keywords I can further research?
It's basically because the leakage current of a transistor in a DRAM cell is temperature dependent. Here's a typical DRAM cell schematic (taken from that book):
And here's a generic graph of how the leakage current varies with temperature for IC-level FETs
The latter graph is from another book. This is in fact an exponential dependence on temperature (note the semilog plot), well-approximated simply by using the Shockley diode model. The book says that "a common rule of thumb is that leakage current doubles for every 10C increase in temperature".
The answers here are good regarding how in normal practice the bitlines will be charged to VDD/2. However that doesn't really answer the question, because it:
does not apply all the time (depends on the cache requirements and process technologies. I have seen plenty of caches that precharge to VDD because at low voltage operation VDD/2 can be too risky)
The 'canonical case' everyone learns first doesn't precharge to VDD/2, and this is the situation he is asking. There is still a good reason they go to VDD, though.
The main reason they charge the bitlines HIGH (in the circuit he is showing) and let them discharge is because the pass transistors are NMOS. This means they pass a very solid '0' but they pass a degraded '1'.
So rather than start the bitlines low and let them pull up through the NMOS (slower and weaker, can only pull to VSUPPLY-VTH), they will start the bitlines high and let them pull down through the NMOS (which can pull down more strongly, to a solid '0').
Another very good reason are the constraints on transistor sizing which must be met for proper writability/readability.
Read operation: M1 must be stronger than M5, so that the voltage divider formed between M5/M1 does not flip the bitnode.
Write operation: M2 must be weaker than M5, so that M5 can overcome the feedback loop when writing a '1'.
So, M1 > M5 > M2 (and M3 > M6 > M4). The PMOS are the weakest transistors in the whole cell, why use that to pull up?
On top of that, traditionally NMOS have been faster than PMOS. This is less true today in the lower process technologies (22nm, 14nm, 10nm, etc) but is still normally assumed.
Best Answer
This is addressed in the paper, in the second paragraph of section 3:
As charge leaks from the capacitor, the voltage difference across its terminals goes to zero, and the "ground state" of what you can read afterwards is just the voltage on the other end of the capacitor.