What does edge triggered and level triggered mean

Instructions are made up of a variable number of "words" and those words are made up of bits. In the case of the 8085 architecture, you can have instructions that are one, two, or three words long, and each word is 8-bits. Those bits are divided up into fields based on your instruction set. What fields there are and what those fields mean is usually contextually sensitive based on the value of one field that always has the same meaning. Typically this field is referred to as the "op code." You should read in detail at least chapter 8 of the linked pdf to get a thorough understanding.

In the case of instructions that operate on registers and store their results in a register, the source and target registers need to be identified in some fields in the instruction. In the case of an instruction that adds a constant to a register and stores the result in a register, the registers still need to be identified, but the constant also needs to be encoded in the instruction in its own field. In instruction set architectures, the term "immediate" is often used to mean a "constant value." In case of instructions that read from or write to memory, the location in memory may have to be encoded within the instruction.

That's the basic idea, hope this helps. For future reference, a good search term for questions like this is "Instruction Set Architecture" for your processor.

Edit Re: STA 4200

The STA instruction is described on page 3-61 (pg 117) of this Assembly Language Programming guide for 8080/8085 processors.The three bytes are:

• Byte 1 = OpCode (00110010)
• Byte 2 = Low Address Byte
• Byte 3 = High Address Byte

STA is the "Store Accumulator Direct" instruction, and what it does is copies the value of the Accumulator into memory at the 16-bit address composed from Bytes 2 and 3.

Although an edge is a well-defined moment in time, it is not true to say that level-triggering also does not have a well-defined moment in time. It does. There is a well-defined moment in time when the level of the clock falls, the inputs to the clocked circuit are sampled, and further changes in inputs are no longer admitted.

The issue with level triggering is that while the clock level is high, inputs change the outputs. In circuits that have feedback (the outputs are connected back to the inputs) level triggering causes chaos, because the level is wide enough (half a clock cycle) that the output can feed back to the inputs within the same period.

So by the time the well-defined moment occurs when the clock falls and every device is supposed to snapshot and hold it state until the next level, chaos has already occurred and the circuits are in unpredictable states. This is unacceptable. In sequential circuits, we want the outputs produced in clock period \$t\$ to only come into consideration for computing the states of clock period \$t + 1\$. We also want the nice property that we can slow down the clock, and not have the sequential circuit break. In level triggering, slowing down the clock works against us. The more we slow down the clock, the more time we allow for unrestricted feedback.

The first obvious solution which suggests itself to shorten the level to the point that it is impossible for unwanted feedback to occur (and to keep the "on" level short, even if we arbitrarily slow down the clock period). Suppose that we pulse the clock from 0 to 1 and back to 0 very quickly, so that the clocked devices accept their inputs, but the outputs do not have enough time to race through the feedback loop to change those inputs. The problem with this is that narrow pulses are unreliable, and basically require a response that may be several orders of magnitude faster than the clock frequency. We might find that we need a pulse that is a nanosecond wide, even though the system runs at only 1 Mhz. So then we have the problem of distributing clean, sharp, sufficiently tall nanosecond-wide pulses over a bus designed for 1 Mhz.

The next logical step, then, is to have the devices generate the narrow pulse for themselves as the time derivative of the clock edge. As the clock transitions from one level to another, devices themselves can internally generate a short pulse which causes the inputs to be sampled. We do not have to distribute that pulse itself through the clock bus.

And so you can basically consider it all to be level-triggered in the end. Edge triggering is a trick to allow devices to create a very fine level trigger which is faster than all external feedback loops, allowing devices to accept inputs quickly, and then close off the entrance in time before their changing outputs will change the values of the inputs.

We can also make an analogy between the "enable" signal (level triggered clock) and a door on a craft which holds air pressure. Level triggering is like opening a door, allowing air to escape. However, we can build an air lock which consists of two (or more) doors, which are not open simultaneously. This is what happens if we split the level clock into multiple phases.

The simplest example of this is the master-slave flip-flop. This consists of two level-triggered D flip flops cascaded together. But the clock signal is inverted, so the input of one is enabled while the other is disabled and vice versa. This is like an air lock door. As a whole, the flip flop is never open so that the signal can freely pass through. If we have feedback from the output of the flip-flop back to the input, there is no issue because it crosses to a different clock phase. The end result is that the master-slave flip-flop exhibits edge-triggered behavior! It's useful to study the master-slave flip-flop because it has something to say about the relationship between level and edge triggering.