Electronic – What does it mean by “storage clock” of a shift register

How is the shift-register wired? Do you have a 0.1uF bypass capacitor across the power leads close to the IC package?

It sounds to me like a noise issue, particularly since it's only triggered when you have a load on the relays. The fact that it results in the shift-register register-state getting reset makes me think it's a power issue.

Also, how are you wiring the shift-register.
With a 74HC595, you need to:

• Tie the two register clocks together (Pins 11 and 12)
• Pull the master-reset pin high (tie pin 10 to VCC)
• Pull the output-enable line low (tie pin 13 to ground)

Lastly, you need a 0.1 uF bypass capacitor between pin 16 (Vcc) and pin 8 (Gnd).

Your idea about programmatically setting the clock and data pins is correct. This technique is often called 'bit-banging'. To find out what goes wrong you should post your code.

The 5V / 3.3V issue could very well be your problem. Try to power the HC595's from 3.3V to see how that affects the problem.

The chip in the RaPi has some dedicated hardware that can be used to interface to SPI peripheral like the HC595. But unless you need to shift data out at the maximum speed the use of such a peripheral is not worth the trouble: bit-banging is much easier.

PS you talk about the clock and data pins, are you aware that there is a second clock (hold clock) that you must pulse once per transferred byte, and that there are a few other pins (reset, enable) that must also be kept at the appropriate level?