Electronic – What does register and bus size depend on

busmultiplierregister

So here is a hardware sequential multiplier depicted. Number A is 51 bits width, number B is 48 bits width. I have to choose the most efficient size of buses and registers (optimize according to memory usage).

general multiplier structure

My actual question is: what do these sizes depend on? How should I proceed in this task? I am not looking for exact solution, but at least a hint, because I have no idea where to begin my search for information.

Best Answer

It looks as though the design is supposed to perform a 48x51-bit multiply in 48 steps, with each step either adding the "A" register to the product register or not. It also appears to shift the "A" register, which isn't necessary. If you want to load the B register, start the machine, and then have a result ready to be read, your product register needs to be large enough to hold the entire product (the sum of the two multiplcands' lengths); the adder will have to be that same width if you shift "A" as you're going along. If instead of shifting the "A" register, you have the product either compute (Product >> 1) or (Product >> 1)+(A << 47) as bits shift out from the "B" register, then the adder only needs to add two 51-bit numbers for a 52-bit result.

Note also that for a small increase in complexity, you can double the speed of your multiplier by having the ALU choose among five operations on each step: (Product >> 2), (Product >> 2)+(A << 46), (Product >> 2)+(A << 47), (Product >> 2)-(A << 46), or (Product >> 2)-(A << 47). Look up "Booth's Algorithm" for more information.