A design engineer told me our PCB prototypes would be completed soon and then he would have his assembler "run a panel". Does anyone know what that means?
Electronic – What does “run a panel” mean in the context of PCB/PCBA fabrication
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I'm late to the game, but I'll give it a shot:
1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?
Some fab shops can plate up internal layers. The tradeoff is usually larger tolerance in the overall thickness of the board, e.g. 20% instead of 10%, higher cost, and later ship dates.
2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?
Yes, though inner layers do not dissipate heat as well as outer layers, and if you're using impedance control, they are more likely to be striplines than microstrips (i.e. using two reference planes instead of one). Striplines are harder to get a target impedance; microstrips on the outer layers can just be plated up until impedance is close enough, but you can't do that with internal layers after the layers are laminated together.
3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?
Yes, it is preferred, but it is also difficult. Usually this is only done with the ground planes, by way of stitching vias and mandating that holes and vias connect to all planes of the same net.
4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.
The new IPC standard on current capacity (IPC-2152) holds up well in real life. However, never forget that the standard does not account for nearby traces also generating comparable amounts of heat. Finally, be sure to check voltage drops on your traces as well to make sure they are acceptable.
Also, the standard does not account for increased resistance due to skin effect for high-frequency (e.g. switching power loop) circuits. Skin depth for 1 MHz is about the thickness of 2 oz. (70 µm) copper. 10 MHz is less than 1/2 oz. copper. Both sides of the copper are only used if return currents are flowing in parallel layers on both sides of the layer in question, which is usually not the case. In other words, current prefers the side facing the path of the corresponding return current (usually a ground plane).
5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?
It's best (and usually easier from a practical point of view) to spread the stitching vias out. Also, there is an important thing to keep in mind: mutual inductance. If you place vias that carry current flowing in the same direction too close to each other, there will be mutual inductance between them, increasing the total inductance of the vias (possibly making a 4x4 grid of vias look like a 2x2 or 1x2 at decoupling capacitor frequencies). The rule of thumb is to keep these vias at least one board thickness from each other (easier) or at least twice the distance between the planes the vias are connecting (more math).
Finally, it is still wise to keep the board's layer stackup symmetric to prevent board warpage. Some fab shops may be willing to go to the extra effort to fight the warpage from an asymmetric stackup, usually by increasing lead times and cost since they have to take a couple tries at it to get it right for your stackup.
Advanced PC boards can only be made by little elves in a hollow tree. It is possible for ordinary mortals to make good enough 2 layer board for hobby or prototype purposes, but even that doesn't make sense unless they value their time very little and not look too hard at the cost of screwups due to not having a solder mask, silkscreen, and the hassle of not having plated thru holes.
Anything beyond basic two layer boards requires elven magic. The elves have spent millions on special trees and are constantly watching the process. Due to the combination of up front cost and special magic, even the elves can only afford to do this by making boards for lots of people to get the volume up and the average cost per board down to less than a pot of gold.
Fortunately the elves have gone high tech and there are now quite a few places on the internet where you can upload Gerber and drill files and receive finished boards usually within a week or two, all without having to dig deep into your own pot of gold. For example, you can get however many boards fit into 75 square inches for $250 at Gold Phoenix. This includes solder mask on both sides, silk screen on one side, of course plated holes, and electrical testing. 8 layers will be more difficult since that is past most place's prototype process, but setting up your own process will be more difficult to.
This is a case where DIY really just doesn't make sense. Are you going to refine your own silicon too?
Best Answer
Like Olin said.
Making a layout of the PCBs on a panel is called a panelization. In most cases V-cuts will be made between PCBs, so they can easily be separated by bending the panel. Care must be taken with high components (e.g. connectors) close to the edges, that they don't prevent the bending.
Alternatively a panel may be milled so that the PCBs are only connected at a few points. These connections are perforated so that they are also easily separateble. Milling is more expensive but may be required for the PCB; they are more precise than V-cuts, and also if your boards isn't rectangular you'll have to mill the edges.
A panel will at least have a couple of edges on opposite sides where the PCB manufacturer will place fiducials.
These are small marks, as copper circles, which are used by the pick-and-place machine as reference points to know where the parts should be placed. Here there are just 4 fiducials on the edges, but I've seen them as two rows at the top and bottom of the panel.
Panels will often have a number of identical PCBs, but you can make a panelization of different PCBs: