Electronic – What does the 8086 CPU do with the data returned from an address in RAM

computer-architecturecpuramx86

I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of.

Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its next instruction from RAM (also with a 16 bit data width). As the CPU fetches the instruction, say at 0x44AB, what exactly does RAM return? Is it an 8 bit op-code and an 8-bit operand? Does it return a 16 bit op-code, and then the operand is stored in 0x44AC?

In the first case, operands cannot have a value greater than 0xFF (255), but then why would you have 16-bit registers? In the second case, the program counter must be incremented by two between each instruction, and you use twice as much memory.

So how does this work? The question might seem a bit vague, but all I'm asking is really what the CPU does with the data returned from an address in RAM.

EDIT: Made the question more specific so that it's easier to give a good answer.

Best Answer

Neither, as for the 8086 CPU, program code is just bytes of data in memory, and the bitness of registers have almost nothing to do with opcode length, as you can move bytes or 16-bit words, and also far jump to a 32-bit address (defined by segment and offset).

As the 8086 is a CPU with a 16-bit bus and the opcodes can be 1 to 6 bytes long, the opcodes may or may not be aligned in any way to the memory. However a typical optimization (manually or by compiler) is to place 16-bit variables and targets for code jumps at even addresses in the memory.

That is because the bus is 16 bits wide, so it must have 16-bit memory at each even memory address, and all odd memory addresses are simply the high 8-bit part of the 16-bit bus.

So, if there is a command which tells the CPU to go execute code at 0x44AB, which is an odd address, the CPU Bus Interface Unit (BIU) will first read one 8-bit byte from that address into the prefetch queue, and continue fetching 16-bit words at a time from address 0x44AC onwards into the prefetch queue.

The CPU Execution Unit (EU) will simply take bytes from the prefetch queue, or wait for bytes to appear if it is empty, and then decode the opcodes and takes any amount of bytes necessary from the queue to fully decode the opcodes.

If you do want to access read or write 16-bit word on odd addresses, the BIU has to do two 8-bit accesses. It needs to access a byte at the high part of 16 bits of a memory location, and the other byte at the low part of 16 bits of the next memory location.

Related Solutions

ISA efficiency code compaction and memory traffic

As a hint to get you started, here are some possible instruction sequences for the first HLL statement:

Accumulator-based

load A
add B
store A

Stack-based

load A
load B
add
store A

Memory-to-memory (2-address)

add B, A

Register-based

load A, r1
load B, r2
add r2, r1
store r1, A

Your job is to figure out how big each instruction is, and also what the memory access patterns are for both instruction and data operations as each sequence executes.

Electronic – Does a CPU completely freeze when using a DMA

You are correct that the CPU cannot be accessing the memory during a DMA transfer. However there are two factors which in combination allow apparent parallel memory access by the CPU and the device performing the DMA transfer:

The CPU takes multiple clock cycles to execute an instruction. Once it has fetched the instruction, which takes maybe one or two cycles, it can often execute the entire instruction without further memory access (unless it is an instruction which itself access memory, such as a mov instruction with an indirect operand).
The device performing the DMA transfer is significantly slower than the CPU speed, so the CPU will not need to halt on every instruction but just occasionally when the DMA device is accessing the memory.

In combination, these two factors mean that the device performing the DMA transfer will have little impact on the CPU speed.

EDIT: Forgot to mention that there's also the factor of CPU cache, which as long as the code that the CPU is executing is in the cache then it won't need to access real memory to fetch instructions, so a DMA transfer is not going to get in the way (although if the instruction needs to access memory then obviously a real memory access will take place - potentially having to wait for a break in the DMA device's use of the memory).

Best Answer

Related Solutions

ISA efficiency code compaction and memory traffic

Electronic – Does a CPU completely freeze when using a DMA

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