Electronic – What does this VHDL code do

vhdl

I was looking over some code that implemented a circuit using an "explicit enumerated state" VHDL implementation.

I am confused as to what this code snippet does, my confusion is syntax related so any help deciphering VHDL here would be great:

case state is 
   when SO => state <= S1;
   when S1 => state <= S2;
   when S2 => state <= S0;
end case;

Best Answer

Add some line feeds and it becomes fairly self-evident:

case state is 
   when SO => 
     state <= S1;
   when S1 => 
     state <= S2;
   when S2 => 
     state <= S0;
end case;

What it does is schedules state to be set to the next state, rotating from 2 back to 0. So S0->S1->S2->S0... If it is not within a clocked process, it will go as fast as it can forever, which is most likely not what you want to happen.

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