Electronic – what exactly is single cycle instruction architectures

assemblycomputer-architecturemips

I got the following text from lab work 2 of CMU's computer architecture course. I am actually trying to do this lab myself out of own interests and I am in no way a student of CMU.

The machine has a single-cycle microarchitecture: every instruction
takes exactly one cycle to execute. Aside from correctness (as de ned
by the architectural speci cations), this is the only constraint that
we are placing on the machine's microarchitecture. As long as these
two constraints are satis ed (i.e., correctness and single- cycle),
you are free to implement the microarchitecture in anyway you want. To
guide you along the way, we provide an abstract description of the
single-cycle microarchitecture as we discussed in class.

  1. The architectural state of the machine (excluding memory) is stored
    in registers: the program counter and general-purpose registers
  2. There is a global wire called the \clock" that is connected to all
    the registers.
  3. When a register sees a rising edge on the clock, the register
    captures the instantaneous \snapshot" of the values on its input.
    From then on, the register holds the captured values and feeds them
    to its output.
  4. The output from the register(s) are fed into a combinational circuit
    consisting of logic gates (e.g., ADD). In turn, the output from the
    logic gates are fed back as input to the register(s).
  5. At the next rising edge on the clock, the register again captures
    the values on its input

.

My doubt: It asks me to implement single cycle architecture but the points numbered from 1 to 5 doesn't seem to be single cycle.

Assume the instruction ADD R1, R2, R3. According to the steps from 1 to 5 this will take two clock cycles and not 1 clock cycle.

  • At the pos-edge of a clock cycle, the address (address in register
    file)registers R1 and R2 will be latched and the values in these
    registers will be sent to ALU for addition.

  • In the next pos-edge, the output of ALU will be written back to regiSter R3.

So it is actually taking two cycle right? EThen why is it called as single cycle instruction?

Best Answer

The only way I know to make read and write happen in the same clock cycle is for register reads to be triggered on positive edge and register writes to be triggered on negative edge(or vice versa), and then to make it so that your data path logic fully propagates within a half clock period. In a single cycle architecture, it's really just a semantic difference, a bit of trickery.

In more sophisticated clocking schemes, you might actually have multiple clock phases, so the 'edge triggering' relationship need not be symmetric as I've described it. When your core is pipelined, this actually matters for correctness purposes so that you don't have a race between your register read and writeback stages.

I think you are justified in being confused about how reads and writes are related in the register file, but that requires you to dig a bit deeper into the transistor level implementation of a single-bit register. I think you will find that there is a race if both events (read and write) are triggered by the same clock edge and your combinational logic can propagate a change before the register state is fully latched. Have a look at this webpage for a logical deconstruction of an edge triggered D flip flop.

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