Electronic – What problems could occur when chaining 40 shift registers

emcnoiseshift-registersignal integrity

I'm planning on chaining together 40 x 74HC595 shift registers. The whole chain of 74HC595s will be controlled by a 5 V microcontroller, which will generate the SDI, CLOCK & LATCH signals.

Each shift register and the microcontroller will have its own PCB, as illustrated in the diagram below:

diagram

Because of mechanical constrains, the distance between each shift register will be of about 30 cm (12 in), so the control signals will travel along a distance of aprox. 12 m (40 ft). Besides that, the whole system will be mounted in a very noisy environment (near fluorescent lights, mains wires etc.)

My concern is that the control signals will be very noisy and the shift registers might output the wrong things. I was thinking of:

  • Using a buffer IC on each board, to buffer the control signals. Which one would you recommend?
  • Using shielded cables between the boards for the signals
  • Lowering the CLOCK frequency as much as possible. I only need to update the registers' content a few times a day.

Are the above solutions a good thing to do? What else can I do to keep the (potential) noise in the signal wires to a minimum?

Best Answer

Use Schmitt-trigger buffers at the inputs of each board. They will clean up the signals so that any noise won't give false pulses on the clock, for instance. The 74LVC3G17 is a triple non-inverting buffer.

Also, pass the buffered signals to the next board. Otherwise all inputs would be parallel and you may exceed the fan-out of the driving microcontroller (I'm especially thinking of the total capacitive load). The daisy chain of clock and latch signals will give a ripple delay throughout the chain, but the data will do so as well, and you plan to go for low speed anyway.