Just curious about early IC history. Wikipedia tells about IC nodes starting with 10 micron, but I'm curious what people produced before that, in 1960s.
Electronic – What were gate length of early SSI circuits
historyintegrated-circuit
Related Solutions
Montgomery Phister's textbook "Logical design of digital computers" from 1958 (written in 1957) introduces the D flip-flop as "the delay memory element".
This doesn't prove anything but it suggests that already in 1957, at least, there was tradition to suggest that the D means "delay".
As a side-note to put things into historical perspective, here's a schematic for a flip-flop from the same book, using radio tubes and 200 volt anode voltage.
Too give the best chance of a device working as expected in an asic cell library we used to work in a system of increasing abstraction.
The spice models for the technology would be written based on mos transistor theory and verified against a test chip which contained a few devices. The Transistor theory always seemed to be fairly accurate but we were not dealing with sub micron technology with a bunch of secondary effects at the time.
This spice model would be used to develop the rest of the cells in the library. These cells would be put on a test chip. This would be manufactured out at the "corners" of the technology. This involves deliberately introducing manufacturing variation (doping,geometry etc) to give fastest and slowest cases. The test chip would be evaluated to produce the digital simulator models which would be used for individual device design.
I don't go back to the days of rubylith but I can remember doing manual checks of cell connectivity on coloured transparent prints (one per layer) before computer CVS (connectivity verification by computer). Took a few days for a 3k gate asic.
In the earlier days when the whole thing was done by cutting rubylith getting and measuring the right dimensions was critical, but the devices were very simple. In the early days of CAD the cells were put down as cells in cookie cutter form and by that stage we were able to assume that the computer generated geometries within a cell and for connectivity were correct.
Related Topic
- Electronic – history of edge-triggered D flip-flop design using three S-R latches
- Electronic – What device/component from the early 1940’s can listen to only a specific narrow range of acoustic frequencies
- Electronic – History of choice of ‘Z’ to represent high impedance
- Electronic – When were tantalum capacitors first used in computing
Best Answer
1960s ICs generally did not have gates, as they were bipolar. NMOS, PMOS and CMOS came into their own in the 70s. So we have to talk about feature size. Early TTL (1960s) was around 12um. There's an interesting (and freely available) IEEE publication reviewing predictions. Here is a relevant chart:
So around 1960/62 we have about 25um and a few um in the early 1970s.
The feature size did not decrease as dramatically as the number of devices increased. More of the improvement was from increased chip size and better use of the available space, all of which together accounted for Moore's Law.
Keep in mind also that most of the applications in the 1960s were driven by military/aerospace programs and were not necessarily subject to the usual rules of economics (Moore's law refers to the most economical number of devices/chip).