It's only a theoretical question; no particular circuit needed.
Some backstory: Suppose there are, say, two NMOS transistors with different W/L ratios in series. Further, suppose that both of them have their gate voltages equal, and their corresponding drain and source voltages. Neglect body and channel length modulation effects. Assume both are in saturation voltages.
The current in first NMOS: Id1= (W1/L1)* kn' *(Vgs – Vt)^2
The current in second NMOS: Id2= (W2/L2)* kn' * (Vgs – Vt)^2
All the terms in both the equations are equal except the W/L ratios.
My Question: When individually calculated, the drain currents of both the transistors are different. More specifically, the drain current is higher in the transistor with higher W/L ratio, and smaller in the other one. But, when both of them are in series, what would be the actual/total drain current in the circuit? Will the current be equal to Id1 or Id2 or something else?
I'm still posting a link of a random figure(ignore the PMOS circuit) for a better idea:
http://ece-research.unm.edu/jimp/vlsi/misc/IMG00002.GIF
Best Answer
You would not be able to control both series source-drain voltages simultaneously. Try to draw out this circuit, with the controlling voltage sources in place. You would need to control both FET's to have the same Vgs and Vds. Once you attempt to draw it out you will realize that it cannot happen (falstad circuit simulator is nice for this, you can probe V and I, in real time).
If you attempt to do this (set both transistors Vgs and Vds simultaneously), you will not have a series circuit, since the voltage supplies would be in parallel. In this situation, the power supplies would source/sink whatever currents were needed to make the FET's Vds equal, but equal currents would not flow through each FET.
In series, there will be more voltage drop on whichever FET is weaker. This provides equal current to the FET which is stronger (with lesser Vsd drop). If one (or both) FET must go into the linear region for this to occur, it will.
Two transistors in series with different W/L ratios combine exactly like parallel resistors. This makes sense because the W/L ratios can be considered as a conductance.
As two numerical examples, consider two similar FET's with the same W/L = 2
If these FET's are placed in series, the 'equivalent' single FET W/L is ~2//2 = 1.
Now, consider two similar FET's with W/L of 1 and 2. The equivalent W/L, if these devices are placed in series and driven with the same gate signal, is ~1//2 = 0.66
So, adding a similarly driven strong FET in series with a weaker FET just makes the chain weaker overall.
Of course there is the body effect (if these are built on-die, which is implied since you can vary the W/L), which increases the threshold voltage of whichever FET's do not have their source at the most negative/positive voltage, for NMOS and PMOS respectively. This can be thought of as reducing the W/L ratio. This occurs if you have two or more of either type in series (2+ NMOS or 2+ PMOS). A CMOS inverter does not suffer the body effect since both NMOS and PMOS have their sources at the respective supplies.