As far as I know there are two major buses – AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real (ASIC) implementations of Wishbone?
Bus requirements:
– patent/license free;
– can connect endpoints with arbitrary bit sizes (e.g. 64 bit to 32 bit);
– fast (can be used to interface ddr3 controller)
Best Answer
Definitely AMBA.
Wishbone has synchronous writes and a-synchronous reads whilst AMBA has both synchronous. In an SOC design you want everything to be synchronous.
On Wishbone you continuously have to add in a wait cycle for the data to come back from a register or from memory*, whilst in AMBA the data flows without waiting.
The write cycle in AMBA is less adapted but:
1/ You read a lot more then you write in SOCs
2/ You can delay/store a write address, but you can't predict read data.
Between AXI/AMBA, AMBA the simplest to implement. AXI is nasty as it looks so simple but is difficult to get right.
*All on-chip and on FPGA memories are synchronous these days.