I'm accustomed to seeing clock speeds on computers in the 1-5 GHz range, or 1.0 to 0.2 nanoseconds (1000 to 200 picoseconds (ps)). This has generally meant that, depending on complexity, logic gates are operating at 5 to 20 times that fast. So a 5 GHz system clock might used for a path of logic with switching times of 40 to 10 ps.
In a 2002 paper on FinFET devices, I see transistor gate delays like "0.34ps for n-FET and 0.43ps for p-FET." Admittedly, these are aggressive numbers, but this is an order of magnitude smaller than the switching times I am imagining.
This leads to me believe that transistor-level switching times and gate delays are not the same thing. What accounts for the difference? And do I have very bad assumptions somewhere?
Best Answer
Clock speeds for logic have to satisfy the full logic margin of the design. The logic output load will be a small-integer number of other logic gates' inputs. Switching times for transistors are commonly measured by making a ring oscillator, and measuring the oscillation frequency.
Ring-oscillator oscillation frequency is not the worst-case over temperature and power variations, does not necessarily mean that the transistors have made a full logic-level excursion, and implies the power gain of the transistor is almost exactly '1', which is inadequate for a gate that has to drive multiple other gates (instead of one subsequent transistor in the ring oscillator).
The speed difference you see in the literature relates to the difference in test methods.