switch-mode-power-supply
While reading schematics diagrams from several switch mode power supplies of LCD TVs, I noticed that the pin which delivers the PWM pulse to the gate of a MOSFET has a diode and resistor in parallel.
Some diagrams don't have it. But there are lot of which they have it. I guess it's some protection to the driver to the IC controller.
Although I'm not sure. In first diagram there are diode and resistor in parallel, and in second there is not.
Madmanguruman and David Tweed are probably on the right track here.
Here is a scenario:
When the circuit starts the synchronous FET (T2) will be on. It has to be this way because there is no bias voltage for the high side drive for T1 except through T2. So, T2 sinks current from the battery through the inductor. Then finally T2 turns off. It doesn't matter if T1 turns on or not, the inductor dumps current back through T1 (or its body diode). The current has to go some place. SMPS are 1 quadrant devices (almost always), so the Laptop supply sinks nothing. The current can only go into C5 and Vcc of the IR2104, which has a max supply voltage rating of 25V. Boom.
Yes, there are stability issues and a brief moment when both FETs are on but the beauty of using a FET on the pull-down part of the circuit (i.e. a synchronous buck converter) instead of a schottky diode is this: -
I'd also advocate building a 555 timer sawtooth generator as the basis of your system. Something like this: -
I'd then feed it into a fast comparator and then the use the comparator output to drive the two FETs. The two FETs can be "time segregated" with a small RC time delay on the output of the comparator - the undelayed output and the delayed output would feed an AND gate for one of the gate drives and the the same for the other gate drive but using a NOR gate. Plan on maybe 50ns time delay introduced.
What you get is a half-decent synchronous buck convertor that just needs an input to the other comparator input to get the required duty cycle changes. OK so far? Then you can apply a simple control loop that lowers the 2nd input to the comparator as the input voltage gets bigger. Get this working and then apply another small control loop that actually regulates the PWM with load current changes a tad and this would probably work and no negative feedback involved.
Then, as the final touch, and with care and subtlety apply an overall control loop to keep the output better stabilized but remember, with a sync buck you can pretty much get half-decent stable performance without control loops that use negative feedback - if you are wanting to go this approach I can recommend it.
However, for me, I'd just call on Linear Technology and get the device that already does the job.
Best Answer
The idea is to get the MOSFET to turn off more quickly than it turns on. When the MOSFET is driven "on" the gate charge is supplied through (say) R915 + R917 = 51.7 ohms.
When it turns off, the gate charge is sucked out through the diode in series with the 4.7 ohm resistor.
You can think of the gate as looking a bit like a large capacitor (gate-source capacitance plus a typically much larger component from the drain-gate capacitance, the latter has a bigger influence due to the Miller effect- the drain typically changes in potential by a much larger amount, multiplying the effect of the drain-gate capacitance.
In the case of the FMV111N60ES, the gate charge can be as much as 73nC.
This can be used to help prevent two MOSFETs from being "on" at the same time, causing shoot through (which wastes power and can damage the MOSFETs) or just to control the waveforms a bit better.