Electronic – What’s the point of board-internal differential pairs

Ok, so I think that I have at least some idea now:

• Considering the 100 MHz signaling frequency, the data and clock signals need to run over transmission lines (assuming a propagation speed through copper of 0.6c, the wavelength is ~1.8m, and using the 10% wavelength rule of thumb and the fact that there is probably higher frequency content in that 100 MHz base signal, it's right in that range).
• In order to minimize signal reflections and other distortions in the line, impedance needs to be as consistent as possible throughout the line. At the frequencies that make it a transmission line, the impedance of the line is dominated by reactance, and more specifically, by the ratio of inductance to capacitance.
• I'm assuming that the inductance of a trace on the PCB will be largely constant for a given length regardless of the layout (excepting funky routing), so the impedance has to be controlled by adjusting the capacitance, which is managed by moving the signal lines closer to or further from the ground plane and/or traces.
• The ground plane is absent under the card edge for three reasons:
  1. The signal pins are wider than the traces, which would result in a higher capacitance between them and the ground plane.
  2. The ground pins add capacitance to the line.
  3. The PCIe connector is built to have the proper impedance as-is, and placing a large ground plane right in the middle would throw off the capacitance, and therefore the impedance.
• I think that the ground pins between the signal pins probably help to reduce crosstalk, but maybe that is a secondary concern?

Am I anywhere close to the right answer, or am I way off? I had looked at transmission lines multiple times and couldn't figure it out, but this answer kind of just came to me after paying more attention to the formula for determining characteristic impedance.

My question is, why should we try to impedance match a differential pair connecting CML devices? Does differential impedance even mean anything since the conductors will never carry equal and opposite signals?

You have to dislocate the DC scenario from the superimposed AC signalling. Numerically the current may not reverse but, as far as sending data down a balanced pair of wires you need a balanced load.

Would it not be better to treat each conductor individually and match them to the single ended impedance of the devices?

However, twisted pair is a tad notorious because it tends to require a balanced load that is not only transverse but longitudanal as well so, your 2nd quote does carry a certain amount of decent weight of truth.

In my experience with +100Mbps data signalling I've tended to fall towards treating a piece of twisted pair as two individual wires and used 2 balanced load impedances connected to screen.