# Electronic – When abstract logic circuits get translated to the electrical equivilant, how are conversions from 0 to 1 handled

digital-logic

I've searched around and there's lots of good information out there, but I'm a bit of a n00b when it comes to the precise meanings of words like current, voltage, amplify, resistor, diode etc. So what at first presents itself as a simple explanation quickly turns into a wikipedia tabfest of ever increasing complexity. With that in mind please forgive my probably inaccurate use of these terms in this post.

The basic problem for me is that gates on a logic circuit appear to be creating power from nothing, which is impossible. For example imagine two NOT gates connected in sequence: To my uninitiated mind what seems to be happening is that the first NOT gate cuts the power to the second NOT gate, which responds by magically conjuring new power out of thin air and sending it on it's way. The only explanation I can come up with feels a bit redundant and absurd (That every single gate on the diagram is implied to be directly connected to a power source)

The closest I've come to an answer is something to do with changing the "signal" from "high" to "low" but again, I'm not familiar enough with the language. It still suffers from the same problem, if you've got a low signal how is it that a NOT gate can turn it into a high one without directly drawing on a power source?

To wrap up and present the question in all it's rookie glory:
How do logic gates physically convert 0 to 1 without violating the law of conservation of energy?

Why do you think it is absurd for every gate to be connected to power source? That's exactly how it works. Here is a schematic representation of a CMOS inverter:

When the input is low, P-channel device is conducts, thus pulling the output high. When input is high, N-channel device conducts and brings output low.

You can also have variants with passive pull-up or pull-down, but none of them "make" power.