I have a situation where reference clock of PLL_0 is coming from some clock source and giving out a clock (named C0) with freq0 and and C0 is going as reference clock to PLL_1 and giving out clock C1 and C1 is going to PLL_2 and giving out C2.
Please see the below figure for better understanding.
simulate this circuit – Schematic created using CircuitLab
In the above situation can we say that clocks C2, C1 and C0 are synchronous to each other?
Note: I would like to add that freq0, freq1 and freq2 are not integer multiple of each other.
To my understanding meaning of "asynchronous"/"synchronous" may vary depending on the context but in very most cases synchronous means that events happen at a fixed phase relation.
So in your case I'd say yes, the clocks are synchronous because phases are fixed (=locked < Phase Locked Loops), although they may have different frequencies and although there may be some small jitter (phase noise).