I've been reading more about proper grounding techniques and using ground planes.
From what I've read, ground planes provide a large capacitance with adjacent layers, faster heat dissipation, and reduce ground inductance.
The one area I'm particularly interested in is the stray/parasitic capacitance created. As I understand it, this is beneficial for power traces but potentially detrimental to signal lines.
I've read a few suggestions about where to place solid ground planes, and I was wondering if these are good recommendations to follow and what would constitute an exception to these suggestions:
- Keep ground plane under power traces/planes.
- Remove ground plane from signal lines, particularly high speed lines or any line susceptible to stray capacitance.
- Use ground guard rings appropriately: Surrounding high impedance lines with a low impedance ring.
- Use local ground planes (same goes for power lines) for IC's/sub-systems, then tie all grounds to the global ground plane at 1 point, preferably near the same place the local ground and local power lines meet.
- Try to keep the ground plane as uniform/solid as possible.
Are there other suggestions I should take into consideration while designing the ground/power of a PCB? Is it typical to design power/ground layout first, signal layouts first, or are these done together?
I also have a few question about #4 and local planes:
- I would imagine connecting local ground planes to the global ground plane might involve using vias. I've seen suggestions where multiple small vias (all in roughly the same location) are used. Is this recommended over a single larger via?
- Should I keep global ground/power planes beneath local planes?
Best Answer
2) I highly recommend AGAINST cutting ground anywhere near high-speed signals. Stray capacitance really doesn't have too much of an effect on digital electronics. Usually stray capacitance kills you when it acts to create a parasitic filter at the input of an op amp.
In fact, it is highly recommended to run your high-speed signals directly overtop of an unbroken ground plane; this is called a "microstrip". The reason is that high frequency current follows the path of least inductance. With a ground plane, this path will be a mirror image of the signal trace. This minimizes the size of the loop, which in turn minimizes radiated EMI.
A very striking example of this can be seen on Dr. Howard Johnson's web site. See figures 8 and 9 for an example of high-frequency current taking the path of least inductance. (in case you didn't know, Dr. Johnson is an authority on signal integrity, author of the much lauded "High-Speed Digital Design: A Handbook of Black Magic")
It's important to note that any cuts in the ground plane underneath one of these high-speed digital signals will increase the size of the loop because the return current must take a detour around your cutout, which leads to increased emissions as well. You want a totally unbroken plane underneath all your digital signals. It's also important to note that the power plane is also a reference plane just like the ground plane, and from a high-frequency perspective these two planes are connected via bypass capacitors, so you can consider a high-frequency return current to "jump" planes near the caps.
3) If you have a good ground plane, there's pretty much no reason to use a guard trace. The exception would be the op amp I mentioned earlier, because you may have cut the ground plane underneath it. But you still need to worry about the parasitic capacitance of a guard trace. Once again, Dr. Johnson is here to help with pretty pictures.
4.1) I believe that multiple small vias will have better inductance properties since they are in parallel, versus one large via taking up approximately the same amount of space. Unfortunately I cannot remember what I read that led me to believe this. I think it's because inductance of a via is linearly inversely proportional to radius, but the area of the via is quadratically directly proportional to the radius. (source: Dr. Johnson again) Make the via radius 2x bigger, and it has half the inductance but takes up 4x as much area.