Electronic – Where is the benefit in SQI parallel interface over SPI? Parallel vs. serial

avrparallelserial-busspi

Microchip is offering a number of serial SRAM chips with a communication protocol called SQI which is similar to SPI but with 4 parallel bits written at each CLK toggle.

If you can spend the extra 3 pins this makes sense. You can achieve a throughput of 4 times the rate of SPI.

However there is a catch – SPI is supported by all modern MCUs as a hardware module so it runs automatically and very quickly and CLK rates of several MHz are not a problem.

SQI is not supported by hardware so you have to bit bang the protocol. If my MCU, for example, runs on an 8MHz system clock and it is executing most instructions in a single cycle (AVR) I can expect SQI CLK rate of under 1MHz. This is based upon software SPI implementation which is also sub 1MHz and has slightly less code in it.

So let's say I can transfer 4 bits at a time, using SQI, with 800 KHz CLK (real world numbers), that is 3.2 Mbits per second.
However I can run SPI at 5MHz and get 5Mbits of data with less code and without having to wait with my application code while data is being sent or received over the communication lines.

So what is the point here? What am I missing?

Best Answer

SQI is not supported by hardware...

Your premise, while correct for your particular MCU, is flawed in the general case. The MCUs that you have been looking at may not have SQI (which I believe is the same as Quad SPI or QSPI), there are many devices with hardware support for QSPI. (Note that "QSPI" is a confusing acronym because it is sometimes also used for "Queued SPI", which is different.)

For example: Many ARM MCUs (for example, STM32 and Atmel SAM) have a hardware peripheral that can do x1, x2, or x4 SPI and some execute from QSPI storage in addition to using such peripherals for data storage.

Most FPGAs support configuration over master serial (SPI) in x1, x2, or x4 widths. Some can even use dual QSPI flash chips for a full eight bits per clock. See the Xilinx 7 series configuration UG, ctrl-F "quad".

In these applications, the QSPI is not bit-bung, and is therefore four times faster. For your specific microcontroller (and many small 8-bit MCUs), you are correct and you will be better off with a regular x1 SPI flash. With many many microcontrollers, applications processors, and FPGAs, there is hardware support for x4 SPI and it is far faster.

Related Topic