Electronic – Which gate is better in buildiing the Full Adder ? XOR or OR

adderdigital-logiclogic-gates

So this is question asked in one of the exams. As you know there are 2 ways to get the boolean expression for the Sum of the fully adder

Given X and Y are inputs, C0 is the carry from previous adder and C1 is the carry output and S as the sum

one expression

C1 = X.Y + C0(X + Y)

C1 = X.Y + C0( X ^ Y )

is the other expression with an XOR gate (^)

so which expression is better in building the Full Adder? Should we use the XOR or OR? and reason for the selction?

EDI:
I previously mentioned it as sum which is a mistake, it's for the carryout

Thank You

Best Answer

If I were doing a silicon implementation, I would use an XOR because of the symmetric properties. Symmetric circuits use much less power because the stack size is the same that does a few useful things:

  1. Greater effective serial resistance when "off" due to the "stack of 2",
  2. Better matched channels because DIBL is the same on pull up and pull down networks,
  3. More uniform switching time because charge sharing is similar (very dependent on #2),
  4. Usually, better devices as far as lithography so better threshold matching.

A very complete discussions exist for "mirror adders" if you look out there, but they probably only mention #1 and #2.

If you have it in a package, none of this matters.

One thing that will not be in the discussions will be that at smaller feature sizes, we try to do everything as symmetric as possible because of metal rules and coloring. Below is an export image of an XOR from a commercially available FinFET process at 14nm that illustrates the metal coloring. The blue/lighblue are different lithography steps.

XOR layout image

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