Electronic – Why are BJTs more reliable than MOSFETs under severe weather conditions

The 741 is an old piece of junk, primarily used to teach basic electronics for cheap. I seem to remember reading somewhere that if every 741 ever made were to be collected, there would be enough to give every person on earth 6 or 8 of them.

Modern op amps fall into several categories.

1. General Purpose - These op amps are not very fast, have bad non-ideal characteristics (bias currents in the nanoamps), drift, have input impedances in the megaohms, and cost almost nothing. The 741 falls in this category.

2. FET Inputs - These are a bit faster, have significantly better non-ideal characteristics (bias currents in the picoamps), drift very little, have extremely high input impedances (gigaohms), but may cost a few dollars.

3. CMOS - CMOS op amps are slow, but have excellent non-ideal characteristics (bias currents in the FEMTOamps), extremely high input impedance (TERAohms), drift about as much as general purpose op amps, and may cost a few dollars. This is the type of op amp that can get its output within millivolts of the rails, but rail voltage is limited.

4. Chopper Stabilized - This is another form of the CMOS op amp. It drifts very little, and has very low offsets. Take a look at this article for more information

There are other op amps out there that can handle RF frequencys, or handle high output currents, but they don't really fall in these catergories.

As you can see, each type of op amp has different non-ideal DC characteristics, and input impedance. How much current flows into the op amp inputs depends on the input impedance. For most modern op amps, these are very small currents, and can be considered negligible for the majority of applications. Which type of op amp you use is a design consideration, factoring in speed, cost, temperature range, and any precision concerns.

Since you haven't specified I will choose my domain of answer: chip design.

The answer really depends ... NMOS is not always better than PMOS in all areas.

Carrier mobility:

• most modern CMOS processes are on <100> crystal orientation wafers. In this system since the transistors are in a common substrate there will be a ~ 2.2X factor in mobility between electrons and holes.

  - however, when they are separate devices like discretes, a different crystal orientation could possibly be used so the mobility argument will be weakened (but electrons will always have better mobility than holes in silicon).
  

• processes around the 65nm node started using stress/strain to more closely match the mobility between the two type of transistors, mainly for size savings. Intel is a prime example of this approach.

Substrate connection:

• Most CMOS processes are on P-type wafers with dual well implants. That means that NMOS transistors have all of their wells at the ground potential (unless they are triple well processes). That means that the bulk connection for a unity gain follower using a NMOS device will be at ground and the back gate effect will be present that reduces the gain to ~ 0.8. When implemented with PMOS devices with the bulk connection tied to the source, the gain can be 1.0.

Noise:

• PMOS transistors at process nodes above 0.35u were typically buried channel devices (due to process techniques used at those nodes). these devices had much lower noise than NMOS transistors in the same process node. Simply because the channel was kept away form the Si/SiO2 interface states at the Si - Gate Oxide boundary. This is particularly true of flicker noise.

• PMOS transistors below 0.25u mostly were surface channel devices and as a result they picked up NTBI (Negative Temperature Bias Instability) noise like characteristics.

Process variability:

• because of the larger sizes required to match the \$G_m\$ PMOS devices are larger and therefore are better matched with fewer effects from LER (Line Edge Roughness).