I've heard that a typical graphics card uses around 100 A of current and only 1 V of voltage. Is there a specific reason why not to use the other way around, so high voltage and low amp? Usually high current leads to high losses, that's why power transmission lines usually prefer high voltage instead of high current. So what am I fundamentally not understanding why that is a bad idea for integrated circuits?
Electronic – Why are integrated circuits powered by low voltage and high current
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No big deal really. First you get a pile of silicon. A bucket of ordinary beach sand contains a lifetime supply if you're going to make your own chips. There is lots of silicon on this planet, but it's mostly all so annoyingly bound up with oxygen. You have to break those bonds, discard the non-silicon stuff, then refine what's left over.
You need very very pure silicon to make useful chips. Just smelting the silicon oxide into elemental silicon isn't anywhere near enough. The bucket of sand was mostly silicon dioxide, but there will be little bits of other minerals, bits of snail shells (calcium carbonate), dog poop, and whatever else. Some of elements from this stuff will end up in the molten silicon mix. To get rid of this, there are various ways, most having to do with very carefully allowing the silicon to crystalize at just the right temperature and rate. That ends up pushing most of the impurities in front of the crystallization boundary. If you do this enough times, enough of the impurities get pushed to one end of the ingot, and the other end might be pure enough. To be sure, you wave a dead fish over it during a full moon while thinking only pure thoughts. If it turns out later that your chips are no good, then one possibility is you botched this step by using the wrong species for fish or that your thoughts weren't pure enough. If so, repeat back from step one.
Once you have pure crystalline silicon, then you're almost done, just another 100 steps or so that all have to be just right. Now cut your pure silicon into wafers. Maybe that can be done with a table saw or something. Check with Sears to see if they sell silicon-ingot-cutting blades.
Next polish the wafers so that they are very very smooth. All the rough stuff from the table saw blade needs to be gone. Preferably get it down to a wavelength or so of light. Oh, and don't let oxygen at the open surface. You'll have to flood your basement with some inert gas and hold your breath for a long time while you finish the polishing.
Next you design the chip. That's just wiring a bunch of gates together on a screen and running some software. Either spend a few 100s of k$ or make your own if you've got a few 10s of man-years free. You can probably do a basic layout system, but you'll have to steal some trade secrets to be able to do the really good stuff. The people that figured out the really clever algorithms spent many M$ doing it, so don't want to give out all the cool bits for free.
Once you have the layout, you'll have to print it on masks. That's just like regular printing, except for a few orders of magnitude finer detail.
After you have the masks for the various layers and photolithography steps, you need to expose them onto the wafer. First you slather on the photoresist, making sure it has a uniform thickness to within a fraction of the wavelength of the light you will use. Then you expose and develop the resist. That leaves resist over some areas of your wafer and not over others, just like the mask specified. For each layer you want to build up or etch or diffuse into the chip, you apply special chemicals, usually gasses, at very precisely controlled temperatures and times. Oh, and don't forget to line up the masks for each layer in the same location on the wafer to a few 100 nm or better. You need really steady hands for that. No coffee that day. Oh, and remember, no oxygen.
After a dozen or so mask steps, your chips are almost ready. Now you should probably test each one to find out which ones hit impurities or got otherwise messed up. No point putting those into packages. You'll need some really really tiny scope probes for that. Try not to breath as you're holding a dozen probes in their targets to within a few µm on the special pads you designed into the chips for that purpose. If you've done the passivation step already, you can do this in a oxygen atmosphere and take a breath now.
Almost done. Now you cut up the wafer into chips, being careful to toss out the ones you found earlier were no good. Maybe you can snap them apart, or saw them, but of course you can't touch the top of the wafer.
You have the chips now, but you still need to connect to them somehow. Soldering on silicon would make too much of a mess, and soldering irons don't have fine enough tips anyway. Usually you use very thin gold bond wires that are spot welded between the pads on the chip and the inside of the pins of whatever package you decide to use. Slap on the top and glob on enough epoxy to make sure it stays shut.
There, that wan't so bad, was it?
Two immediate modes of failure are over-voltage and over-current.
- If you have a high impedance input like a gate to a mosfet, then high voltage (even at very low current) will cause a puncture in the capacitive gate of the mosfet as the electrons have enough energy to cause the dielectric to breakdown. Once this occurs, the resistance of the input drops to near nothing and a later low-voltage high-current will further heat up and destroy the mosfet. This mode of failure is why there is ESD protection on many chips.
- Over-current causes over heating of the device. Once temperatures get high enough to start changing the structure and/or burning of the internal semiconductors, it will start acting funny, working less efficiently, or completely failing as an open or short.
It's possible that you could think of reverse voltage as another failure mechanism, but generally that still falls under one of the other two categories, it's just different to think about. For instance, if someone reverses a power supply on a circuit with a diode in it, they may expect no current through the diode and instead get an over-current condition because the diode would now be forward biased.
Note that capacitors, resistors and inductors (and any other circuit element) are likely to be damaged in similar ways as transistor ICs, i.e. over-current and/or over-voltage.
Other failure modes of electronics in general may be found here: http://en.wikipedia.org/wiki/Failure_modes_of_electronics
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I am not sure why this wasn't the first thing pointed out by any of the earlier answers, but it is because as transistors are made smaller to increase speed, increase density, and reduce power consumption, the gate oxide layer is made thinner (which also increases leakage currents).
A thin gate oxide layer can't withstand very high voltages so you end up with a device that only operates at very low voltages. Thin oxide layers also have more leakage so you don't want a high voltage anyways since that would just increase leakage current and increases static power consumption.
Your mistake is this:
Data processing, unlike power systems, isn't about power delivery; It's about data processing. So it is not that designers choose to operate at low voltages and high currents thus going against \$I^2R\$. Yes, they are concerned about power consumption and heat due to losses, but they aren't concerned with the efficient delivery of power. A power designer has to deliver X amount of power and would increase voltage so they could decrease current while delivering that same power. A digital designer would outright decrease the "power output" if they could.
Their optimizations necessitate low operating voltages which results in high leakage currents. The goal of these optimizations is to allow smaller transistors so you can pack more of them in as well as switch them faster, and when you have millions upon millions of transistors switching very frequently that results a lot of charging/discharging the gate capacitances. This dynamic current results in the high peak currents which can be tens of amps in high-speed, high density digital logic. You can see that all this current and power is undesired and unintentional.
Ideally, we would like really no current at all because our concern is information, not energy/power. High voltages would also be nice for noise immunity but this runs directly counter to making transistors smaller.