I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write and read, how does dqs improve performance of ddr.
Electronic – Why cant clock be directly used instead of DQS in DDR during read and write
ddrdrammemoryram
Related Solutions
Unless your microcontroller has a direct bus support for interfacing to DDR/DDR2/DDR3 type RAM or your microcontroller is interfaced through an FPGA which has been programmmed to provide the RAM interface then it is likely that futzing around with DIMMs is not a useful exercise. There are several strong reasons why this is the case....
1) DDR memory chips may be operating at lower voltages than your microcontroller.
2) The interface to the DDR memory is multiplexed and requires precise clocking whilst the multiplexed lines change states in sync with said clock.
3) Modern DIMMs are designed to operate at very high frequency clocks of 800MHz, 1066MHz, 1333MHz, or 1600MHz. Signal integrity is extremely extremely important when designing the circuit connections to the DIMM. It is not a trivial exercise and the memory chips can be extremely sensitive to noise as a result.
4) DDR memories require constant refresh to keep the memory cells data valid. Without refresh the memory content fades away over time from milliseconds to seconds.
5) The command structure to operate modern DDR RAMs is complex. The most complicated part is getting the initialization sequence correct which consists of some 13 to 20 individual steps.
6) Modern DIMMs are designed to feed data to modern PC type computers very fast. The typical DIMM has a data path width of 64-bits. Multi rank DIMMs also require multiple clocks and chip select signals to access all of the memory chips on the memory stick. It is unlikely that the typical small microcontroller can make effective use of this wide data format without an excessive amount of external circuitry.
Keep this in mind too. Companies that make PC style processors that utilize DIMMs have onboard controllers to interface to the memory sockets. There is an engineering specialty for programmers that work in the BIOS field called MRC (memory reference code). This is the program code module that initializes the DDR controller and all the attached DIMMs. This specialty employs the best and some of the most senior BIOS programmers that do nothing but MRC coding as a full time job.
What is DDR software leveling ?
It is a method to compensate for the signal propagation delays as a result of different trace length at high frequencies.
How it is different from DDR2 and DDR3 ?
It is just a mechanism that is used for (DDR2 and)? DDR3.
Why it is required and important ?
It is intended for fine tuning the DDR interface. For example to be able to use higher frequencies.
There is a seed used for this how this seed is calculated?
The seed values are the actual values that are used to configure the DDR PHY registers in software. In general, the values depend on DDR3 clock frequency and CK and DQS trace lengths. Texas instruments for example provides an Excel spreadsheet for obtaining the seed values.
Generally leveling is required to ensure proper timing for read/write operation is that the only purpose?
As far as I can tell, yes.
Best Answer
DQS is aligned with the data bus DQ, not the clock. It is used to precisely time where the DQ data are to be sampled. It’s a necessary complexity in order to support the clock speeds contemporary DDRx DRAM can achieve, in a way that supports a large number of chips and groups-of-chips (that is, ranks.)
DQS and DQ do have a rough alignment with the input clock, but this relationship isn’t tightly defined - certainly not well enough to achieve the timing accuracy needed to capture DQ correctly.
Instead, DQS and DQ are source-synchronous: they travel together from host to DRAM and vice-versa, and so have the same point-to-point delay. This applies in both directions: on writes the host drives DQ and DQS; on reads the DRAM chip drives them.
And it gets even more complicated. On writes, the host sends DQS phase shifted by 90 degrees and the DRAM catches DQ in the middle of its validity window. On reads, the DRAM sends DQS aligned with DQ, and the host phase-shifts DQS internally using a Delay Locked Loop (DLL) and captures DQ with that internal clock. In both cases the goal is the same: to get the best possible timing margin on DQ.