# Electronic – Why does more bandwidth mean higher bit rate in digital transmission

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I understand that similar questions like this one have been asked before on this site, listed below. However, I am confused about the answers. If I explain what I think I understand, can somebody please point out where i'm wrong?

Shannon Law gives the theoretical upper limit

$$C_{noisy}=B*log_{2}(1+\frac{S}{N})$$

if S = N, then C = B

As N→∞, C→0

As N→0, C→∞

Nyquist Formula says approximately how many levels are needed to achieve this limit

$$C_{noiseless}=2*B*log_{2}M$$

(If you do not use enough logic levels you can not approach the shannon limit, but by using more and more levels you will not exceed the shannon limit)

My problem is that I'm having a hard time understanding why bandwidth relates to bit rate at all. To me it seems like the upper limit of the frequency that can be sent down the channel is the important factor.

Here's a very simplified example: No noise at all, 2 logic levels (0V and 5V), no modulation, and a bandwidth of 300 Hz (30 Hz – 330 Hz). It will have a Shannon Limit of ∞, and a Nyquist Limit of 600bps. Also assume that the channel is a perfect filter so anything outside of the bandwidth is completely dissipated. As I double the bandwidth, I double the bit rate etc.

But why is this? For two level digital transmission With a bandwidth of 300 Hz (30 Hz – 330 Hz), the digital signal of "0V's" and "5V's" will be a (roughly) square wave. This square wave will have the harmonics below 30 Hz and above 330 Hz dissipated, so it will not be perfectly square. If it has a fundamental frequency at the minimum 30 Hz, (so the "0V's" and "5V's" are switching 30 times a second), then there will be a good amount of harmonics and a nice square wave. If it has a fundamental frequency at the max 330 Hz, the signal will be a pure sine wave as there are no higher order harmonics to make it square. However, as there is no noise the receiver will still be able to discriminate the zeros from the ones. In the first case the bit rate will be 60 bps, as the "0V's" and "5V's" are switching 30 times a second. In the second case the bit rate will be a maximum of 660bps, (if the threshold switching voltage of the receiver is exactly 2.5V), and slightly less if the threshold voltage is different.

However this differs from the expected answer of 600 bps for the upper limit. In my explanation it is the upper limit of the channel frequency that matters, not the difference between the upper and lower limit (bandwidth). Can somebody please explain what have I misunderstood?

Also when my logic is applied to the same example but using FSK modulation (frequency shift keying), I get the same problem.

If a zero is expressed as a 30 Hz carrier frequency, a one is expressed as a 330 Hz carrier frequency, and the modulation signal is 330 Hz, then the max bit rate is 660 bps.

Again, can somebody please clear up my misunderstanding?

Also why use a square wave in the first place? Why cant we just send sine waves and design the receivers to have a switching threshold voltage exactly in the middle between the max and min value of the sin wave? This way the signal would take up much less bandwidth.