Electronic – Why does this circuit work

First, \$v_{in}\$ is an AC signal voltage while \$V_{GS}\$ is a DC bias voltage. These are treated separately.

From a small-signal perspective, the current source (lower FET) is effectively an open circuit so there is effectively no voltage division for the AC signal. This is why \$v_{in}\$ appears at the output node unattenuated (assuming the output node is connected to an effectively open circuit).

From a DC bias perspective, the gate of the top FET is at (presumably) zero volts so the source, which must be more positive than the gate, must be at 2.8V (using the values in the book and assuming the FETs are identical).

However, note that this is not \$V_{GS}\$ since, in fact, \$V_{GS}\$ for both FETs is -2.8V. In other words, the voltage at the source of the top FET is $$v_{in} - V_{GS}$$

The circuit employs negative feedback and utilizes the very high gain of the op amp. The op amp will try to keep its non-inverting and inverting inputs at the same voltage \$V_{\text{set}}\$ due to its very high gain. Then by Ohm's law

$$I_{\text{set}} = \frac{V_{\text{set}}}{R_{\text{set}}}$$

Negative feedback causes the op amp to adjust the transistor base voltage so that \$I_{\text{set}}\$ is constant even with a varying load. If the varying load causes a temporary increase in \$I_{\text{set}}\$ then the voltage at the op amp's inverting input will temporarily rise above the non-inverting input's. This causes the op amp's output to decrease, which lowers the transistor's \$V_{BE}\$ and therefore its \$I_{C} \approx I_{\text{set}}\$.

Similarly, if the varying load causes a temporary decrease in \$I_{\text{set}}\$ then the voltage at the op amp's inverting input will temporarily fall below the non-inverting input's. This causes the op amp output to increase, which increases the transistor's \$V_{BE}\$ and \$I_{C}\$.