mosfetmosfet-driver
Please take a look at this circuit, which I am using purely as an example:
Please can someone explain why, if a battery was attached, does the circuit not short to ground as I drew in the red arrow?
Surely, if and when the "low" side is on, and the "high" side (HIDRV) mosfet off, then there is a short to ground?
There are a number of uncertainties in what you say you are doing. You need to stabilize the patient and understand what is really going on in order to make progress. At present there are several things wrong which are obscuring each other. Being able to deal with each ne in isolation makes life much easier.
(1) Your sentence below does not make sense. Can you please explain more clearly what you mean. "The MOSFETS are connected" and "drain and source ... connected" can both mean the same thing. If they DON'T mean the same you need to explain what you mean. You said:
(2) This would be fatal:
As Oli says, presumably you mean Vdd = Vcc. You need to read what you write before sending. We all need to and we all get it wrong sometimes BUT when you are asking the questions and want help then confusing the assembled masses with typos is a very bad idea.
(3) This probably means that your IC is dead or walking wounded OR you have a disconnected line - possibly ground. When things go this wrong you need to carefully measure everything - voltages when on and ohmic connections when off. look for shorts AND opens.
(4) If you were using "real" voltages your IC and random other things would now be dead. Shorting the capacitor connects the isolated high voltage "island" in thje IC to the drain of the lower FET which gets connected to ground when the lower FET is turned on. Shorting this cap could be an extremely exciting and non productive thing to do in many situations. Hopefully you determined before you did this what you expected to happen and didn't just do it to see what happened. When you are dealing with power rather than signal the magic smoke is never too far away. You may have had some already without being aware of it.
(5) Making the capacitor 100 times larger than you calculate in a circuit that may be switching at 10's to 100's of kHz is highly likely to produce interesting results. These could include an interesting emulation of lot's wife. But may not. The capacitor has to charge in the time that the low side FET is on. It discharges when the high side FET turns on. There will be charge & discharge time constants controlled by the resistance in the IC power paths. This may still work OK OR the voltages may only rise to a fraction of what is intended in the time available. Which may be consistent with what you are seeing.
I could add a bit more but that should do to start :-). Sometimes we all have a bad day - you need to try and not let too many things at once get out of control as then you can't asily analyse what is going wrong.
As others (and I) have suggested, measure everything you can and see if it makes sense. If you have an oscilloscope see what it can tell you. If you don't have a'scope, start putting lunch money aside for one. Even a relatively cheap scope can be a mightily powerful tool. An oscilloscope is possibly the most effective and powerful debugging and fault finding aid you will ever have for analog circuits.
Practical aspects:
If hand driving at low speed, connect Hin and Lin and SD low with pull down resistors. Then, if you hand switch them and they "bounce" they will bounce from low to applied signal level and not to some unknown state.
BUT the bootstrap powering circuit for the upper gate completely relies on there being an AC signal at VS to supply AC at Vb which draws power from Vcc and delivers it to Vb. If there is no AC your =upper gate signal will decay "rapidly". How long it takes depends on upper driver power consumption and was part of your capacitor calculations (from memory). This is an example of where an oscilloscope will help you see what is happening. The 100 uF you are using is a large value and decay time may be long enough to see what is happening "by eye", but maybe not.
If you want to drive with a microcontroller you could reduce Vcc to Vdd rather than raising Vcc - as long as IC minimum voltage spec is still met.
Re-etch of PCB MAY be a good idea BUT you should be able to carefully go over circuit and check that what you have is what you intend. Do it pin by pin.Talking to yourself about it as you go can help :-) (really). Describe what you expect to see and what you really see and why they are or aren't compatible. [Watch for men in white coats observing you suspiciously when you are talking to yourself - or do it in your head or, works well, get a knowledgeable friend and explain it to them. The very act of explaining often works wonders.]
IN pin should not be pulled high continuously , this driver is a bootstrap driver , which means it needs to recharge the bootstrap capacitor through the low side mosfet when the high side mosfet is off.
buttom line , IN pin should be PWM from 0 to around 95% but never to 100%.
if you want 100% , ( for some applications you do ) there is solutions like adding a charge pump ... etc
check out this app note from Texas instruments Providing Continuous Gate Drive Using a Charge
EDIT:
After checking the datasheet it seems you have another mistake , that is powering the IR2104 from 5v , the IR2104 accepts 3.3v and 5v and 12v logic inputs at IN and SD , but its supply (aka VCC ) should be above between 10v to 20v. the IGBT voltage can be 5v no problem .
Best Answer
Q1 and Q2 are a pair driving an inductor to form a buck (step-down) DC-DC converter.
There are two phases of operation:
The key is, neither Q1 or Q2 are kept on long enough such that a short can occur; the current though L is a sawtwooth that averages out to the charging current being delivered to the load. This is true so long as Q1, Q2 and the bq24650 IC are working correctly to deliver the charge current.
That said, you're right in observing that if Q2 stayed on, the battery would be connected as a short-circuit through the inductor L. That's not likely as the IC controls the Q2 gate, but it's a possible failure mode to consider.