Electronic – Why does VHDL function declaration not accept bounds for the return type, e.g. std_logic_vector

functionvhdl

I know that in VHDL each function call is instantiated as a separate combinational circuit. I am writing a function that takes in a 4 bit value and returns a 7 bit value from a look up table. The declaration in the package head looks like this:

function my_function(lv: std_logic_vector(3 downto 0)) return std_logic_vector(6 downto 0);

The compiler is generating error. It seems to me that the function declaration cannot include the size of the logic vector. Why? Does the same apply to integers where the range of integer value be given?

Best Answer

This is mostly for Jonathan Drolet but there's also a lesson here. Note that parameter argument to my_function supplies a type mark with a subtype indication. This is valid in VHDL.

library ieee;
use ieee.std_logic_1164.all;

entity myfunc is
end entity;

architecture foo of myfunc is
    function my_function(lv: std_logic_vector(3 downto 0)) 
            return std_logic_vector is  
    begin 
    return lv & "000";
    end function;

    constant fumble:  std_logic_vector (3 downto 0) := x"E";
    signal humble:    std_logic_vector (6 downto 0);
begin
    humble <= my_function(fumble);

end architecture;

This code analyzes, elaborates and simulates.

Note that the return mark is an unconstrained subtype and the result value is assigned to a declared signal with a subtype indication (supplying an index constraint).

There are rules specifically for determining the effective value of a signal that require the bounds be checked after an implicit subtype conversion. Providing a return value that doesn't match the bounds of humble would result in a run time error causing simulation to end without successfully completing.

In other words a constraint isn't necessary here. The return value subtype indication is derived internally, and as is shown in this from the input parameter.

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