fpgaisexilinx
I am using the newest version of Xilinx ISE Webpack(v14.7). every time I try to use fork-join statement ( in Verilog ), I receive this error:
ERROR:Xst:850 : Unsupported Fork Statement.
Is this block type unsupported in Webpack or I am missing something? Here is a very simple example:
Inouts are actually "wire" so you can't use any procedural/sequential assignments (where the left hand side must be a reg). Generally speaking:
A common approach is to have an "enable" signal for the output of your inout, and to drive to high impedance if the output is not enabled. In your case direction is playing that role.
So try this instead:
module test(
input clk, // The standard clock
input direction, // Direction of io, 1 = set output, 0 = read input
input data_in, // Data to send out when direction is 1
output data_out, // Result of input pin when direction is 0
inout io_port // The i/o port to send data through
);
reg a, b;
assign io_port = direction ? a : 1'bz;
assign data_out = b;
always @ (posedge clk)
begin
b <= io_port;
a <= data_in;
end
endmodule
The hardware corresponding to the above code would look something like this:
That Verilog module is top-level, right? Make sure, because the toolchain will try to map the UCF onto the top level module. If you're using a third-party toolchain that "sits above" the Xilinx toolchain, you will want to investigate what top-level file the third-party toolchain is creating.
I looked in my UCF files and I don't see INST at all. I use NET everywhere (with the exception of one TIMESPEC on the main clock)
Another thing I noticed...
always @(posedge clk_ddr or posedge rst) begin
if(rst)
cnt <= 1'b0;
You are using posedge on two different signals. Pin C on FDC probably means the "clear" pin of a D Flip Flop (hence, FDC). You probably actually want an FDCE (D Flip Flop with async Clear and clock-Enable), or an FDE (D Flip Flop with clock-Enable). The synther is probably confused because flip flops only have one edge-sensitive input and you're asking it for a flip flop with two edge sensitive inputs.
Did you want an async clear, or a sync clear? If async, get rid of the "posedge" in front of rst. If sync, get rid of the entire "posedge rst". Async clear (FDCE) is trouble unless you know what you're doing; go for the sync clear (FDE).
Best Answer
As I don't do Verilog, it may be worth waiting for a Verilog expert to answer.
But meantime, wouldn't "fork/join" imply creating processes at runtime? If so, there's no way that will be synthesisable; you can't create or destroy gates on a running piece of hardware. And XST is a synthesis tool... (EDIT: technically gates can be destroyed but outside of fuse-based ROMs or PLDs it's not normal practice!)
Does the documentation happen to mention if this is a simulation-only construct? If so, Webpack probably does support it ... for simulation.
Incidentally I don't understand what "fork/join" is intended to accomplish here. In what I would guess to be the VHDL equivalent:
the assignments to A and B take place simultaneously as explained here , so isn't fork/join redundant, or is Verilog even more different than I thought?