How does Logisim handle xor gates without exactly two inputs? A two-input xor gate should have an output which is true if one input is true and the other is false, but it's not completely unambiguous from just that description how that should be generalized to N inputs. The normal approach is to say that the output of an XOR gate of any size should be true if the number of "high" inputs is an odd number; I would consider any other meaning to be non-standard. Nonetheless, it's possible that Logisim is defining "xor(a,b,c)" as being "and(or(a,b,c), nand(a,b,c))" (meaning at least one, but not all, of the inputs is true). Split the 3-input xor into two cascaded two-input xor's and the circuit should behave normally.
Not with only the standard AND, OR, and NOT gates. For the two-bit adder that takes in two-bit numbers AB and CD, and outputs a three-bit number XYZ, the truth table looks like this:
A B C D | X Y Z
0 0 0 0 | 0 0 0
0 0 0 1 | 0 0 1
0 0 1 0 | 0 1 0
0 0 1 1 | 0 1 1
0 1 0 0 | 0 0 1
0 1 0 1 | 0 1 0
0 1 1 0 | 0 1 1
0 1 1 1 | 1 0 0
1 0 0 0 | 0 1 0
1 0 0 1 | 0 1 1
1 0 1 0 | 1 0 0
1 0 1 1 | 1 0 1
1 1 0 0 | 0 1 1
1 1 0 1 | 1 0 0
1 1 1 0 | 1 0 1
1 1 1 1 | 1 1 0
The Karnaugh map for Y looks like this:
CD AB>
V 00 01 11 10
00 0 0 1 1
01 0 1 0 1
11 1 0 1 0
10 1 1 0 0
The problem is that since you are only allowed two gate delays, and we need both of those: one to AND together the bits in each group, and another to then OR those groups together. This means that the groups we can specify are limited to those that do not contain any NOTs, i.e. only the following:
A B C D A*B A*C A*D B*C
. . x x . x x . . . . . . . . . . . x . . . . . . . . . . . . .
. . x x . x x . . . . . x x x x . . x . . . . . . . x x . . . .
. . x x . x x . x x x x x x x x . . x . . . x x . . x x . x x .
. . x x . x x . x x x x . . . . . . x . . . x x . . . . . x x .
B*D C*D A*B*C A*B*D A*C*D B*C*D A*B*C*D True
. . . . . . . . . . . . . . . . . . . . . . . . . . . . x x x x
. x x . . . . . . . . . . . x . . . . . . . . . . . . . x x x x
. x x . x x x x . . x . . . x . . . x x . x x . . . x . x x x x
. . . . . . . . . . x . . . . . . . . . . . . . . . . . x x x x
Note that none of these groups covers the 1001 spot without covering the 1101 spot, which we need for Y. You may be able to get the correct groups using a NAND, NOR, or XNOR; but only if those count as 1 gate delay.
Note that if you are using a technology like CMOS logic where each bit has an inverse available, then using the Karnaugh map technique renders this problem trivial, with an example solution below (where a is NOT A, etc.):
X = AC + ABD + BCD
Y = Acd + abC + Abc + aCd + aBcD + ABCD
Z = bD + Bd
Best Answer
The ones place of a single-bit addition is equivalent to the exclusive OR operation, not the OR operation. Hence XOR is used instead. Note that this is not the only way to build a half adder, you can do it without using an XOR gate, but it requires more gates.
For example, here is a half adder built with only AND, OR, and NOT gates:
You can see here that an OR gate is used to form the ones place output, but an AND gate is also necessary to turn off that output when the carry output is set.
One thing to note is that these adders are usually implemented not with several separate gates, but as one optimized unit, like this:
The construction with logic gates is just a functionally equivalent version of the actual implementation.