What's the problem?
It isn't clear why you can't use your existing layout and just translate for the bigger package?
Guard rings are about DC...
The guard ring is designed to deal with leakage currents by placing a nearby intermediate voltage between sensitive sources.
The ground plane is for providing the low-inductance return path. If you are moving (returning) a substantial percentage of your signal on the guard ring, something is wrong.
Terminating your guard ring is not a hugely complicated concern, so don't over-think it.
Bypass what exactly?
The load capacitors/oscillator do not need an additional bypass. It doesn't do anything because there is nothing to bypass here.
The power loop for the oscillator includes the power entry pin to the PIC (bypass there), it's internal power distribution grid, the oscillator driver circuits, the oscillator tracks, and the crystal/osc itself.
Your bypass cap at the bottom of the second figure doesn't influence anything in that pathway. The answer you cite deals with a completely different scenario (the power pins of the IC itself, not I/O pins as in your scenario).
What to do:
- Single via at the extremity of the guard ring to ground plane
- Keep the crystal/osc lines as short as possible
- Place the load caps next to the crystal/osc -- turning them so that they are parallel to the long side of the crystal/osc with their ground pins facing each other is a good way to lower inductance, but it isn't critical to do so.
- Pour a small surface ground plane over the ground pads (don't forget thermal relief) and stich to the ground plane underneath with a few vias.
- Escape the nearby PIC pins via fanout and via to the lower surface for further travel (allows the lines to take up less y-space so that the crystal can be placed closer to the chip)
- Regarding C10 in the original figure. Just place it as close to (what looks like to me) pin #38 as possible. Don't worry about a cap near pin #41. It's covered by C10 even if C10 is a little further away.
Good luck! I'll follow-up if you have any further questions. Cheers.
Is it correct to assume that an ideal (theoretical) PSU for audio applications should produce a constant voltage regardless of load variations (i.e. it is a voltage source)?
Yes. An ideal power supply for any application should be an ideal voltage source, which has a constant voltage.
In practice, what are acceptable levels of supply voltage variation due to transients in an audio application (in percentage of Vs or mV)?
This is dependent on your application. You have to evaluate your desired noise/distortion, the power supply rejection of the audio components you are using, and the way the circuit is constructed. 0.1% power supply variation translates to a -60dB noise floor, which might be sufficient.
What is the correct approach to reduce these V swings? Should I place a capacitor on the INPUT or OUTPUT of the regulator? Is there a rule of thumb/calculation for the required capacitance? Are electrolytic capacitors OK, or should I use polyester or tantalum caps (i.e. something with a lower ESR)?
Probably both. You should have both bulk capacitance on the output and low-ESR decoupling caps in close proximity to all active chips (op-amps, ADCs, DACs, etc). And some more capacitance on the input certainly wouldn't hurt.
Typically, you might use large electrolytics for bulk capacitance, and low-ESR ceramics for faster decoupling. Again, how much you need depends on the magnitude and characteristics of the wiggles on the supply rail. Also, carefully read the datasheet of the regulator and make sure you are within its comfortable operating region: the regulator has a response speed and current limits, as well as input ripple rejection specs.
This is true because the LM7815 is stable with any output capacitance- the capacitor is just there to reduce the output impedance at high frequencies. Vout comes from the emitter of the NPN pass transistor.
The LM7915, on the other hand, is made with a similar semiconductor process but has to produce a negative output voltage. Vout comes from the collector of the NPN pass transistor. It's not stable without a largeish capacitor on the output. With only 100nF on the negative regulator it will likely oscillate under some conditions, whereas the positive regulator will be fine.
As far as the AD8099 goes, it probably has to do with the (internal) compensation capacitor being connected to the negative supply. Op-amps do not have ground pins generally.
So, any change of the negative supply pin relative to 'ground' is coupled to the amplifier.
What appears to be a pattern is actually from two quite different root causes.