digital-logicflipflop
I have come across the RS flip flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the unstable or the forbidden case S=1, R=1 in the flip flop. Can anyone tell me what exactly is that?
By the way I have used 2-input NAND Gates to implement the flip flop. What is the difference between the NAND gate flip flop & NOR gate flip flop?
You need to understand that a D type flip flop is a 1 bit memory element. When you give it a set signal it'll store its D input and will output it from the Q output on the fallowing cycles, until the set bit is raised again or the reset bit is set.
So, by putting 2 or more flip-flops together, with the same clock, set and reset inputs what you get is an n bit register, or n bit memory unit.
A diagram for a 2 bit register from flip-flops:
This is of course a volatile memory, meaning it'll lose its value once power supply is cut off.
Also, while this is the way registers are made, for example in the cpu, this is not the way that cache and RAM memories are made.
Problem 1)
Basically start by saying S' is 0, this means that Q will be 1 (as the NAND gate is high when Either A or S' is low), therefore B will be 1. As B is one the inputs to the second gate are 1 and 0 therefore Q' is 1. So A will be 1. The inputs to the first gate will be 1 and 0 so Q will still be 1.
Problem 2)
A will change from a 0 to a 1 but Q will still be high as S' is still 0
Best Answer
Assume ideal logic gates (no propagation delay) like this (image from wikipedia):
We know that the output of NOR gate is 1 if and only if both inputs are 0; and 0 otherwise.
When S = 1, Q = 1 and therefore \$\bar{Q} = 0\$; when R = 1, Q = 0 and \$\bar{Q} = 1\$.
But if you set both R and S to 1 we have that Q = 0 and \$\bar{Q} = 0\$ at the same time. This contradicts the relation \$Q = \bar{Q}\$. In the real world one of the gates will reach the 1 state first and the result will be unpredictable.
For the NAND-based RS flip-flop the same can be shown when R = S = 0, by writing the logic equations appropriately.