Electronic – Why Verilog doesn’t introduce a FF for reg type variable in always@* block and why reg is allowed in combinational circuits

verilog

as far as I know, register (e.g., reg reg1) and register file (e.g., reg [3:0] reg2)

can be used in the always block whether it is a sequential (i.e., always @(posedge clk)) or combinational (i.e., always @*).

However, only when they are used in sequential always block, Flip-flops are inferred.

I think it's because register and register file in combinational always block are assigned continuously, so memory may not necessary.

However, I don't know why Verilog allows using register and register-files inside the always @* block which is a combinational circuit.

Is it because to enable RT level description such as if statement, case statement, etc in combinational logic?

The name 'reg' confuses me because its name implies the storage (FF), but it acts like a just wire inside the always @* block.

It seems that the 'reg' works as expected as a storage only inside the sequential always block.

Even though assign keyword allows a value to be assigned to a wire variable,
is there any other reason that the Verilog allows register and register files to be used inside always @* block as a wire?

To me, a register and register file are just declared as a reg type in combinational always block to be used at LHS of assignment, but act as a wire type variable.

I appreciate any help.

Best Answer

However, I don't know why Verilog allows using register and register-files inside the always @* block which is a combinational circuit.

Because designating a signal as reg or wire has nothing to do with whether it is implemented as the output of a register or a combinatorial circuit. It only relates to whether the signal can be assigned to by a procedural assignment (assignment in an initial or always block) or by a continuous assignment (assignment by an assign or instance output).

Reg signals can be assigned to in procedural blocks. Wire signals can be assigned by continuous assignment. That is absolutely all the different signal types mean, and this is simply something you have to get used to when working in Verilog.

The names seem to imply a different meaning because Verilog was originally intended to be a tool for modeling hardware that was designed by other tools rather than a tool to synthesize new designs, and so using it for synthesis has a few warts that reflect the inherent kluginess of doing that.

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Electronic – Beginner with fpga and timing issues

Have I understood that situation correctly?

Yes - if some part of your output data is available later than other parts, you have to delay the other parts so they line up.

It's not a fudge, or a "bad" thing to do - it's just what has to be done to make the outputs right.

I could probably buffer the sync pulses too and delay them in the same way.

That's what I'd do. (EDIT: And as Yann reminded me, delaying signals can be very cheap in Xilinx FPGAs - 16 ticks can fit in a single look-up table + 1 more in the flipflop that's next to the LUT)

Or I could pre adjust the calculated memory address to compensate in advance.

That's another option, but will probably take more logic.

Electronic – Verilog: Check for two negedges in always block

The always@ is a sensitivity list and generally not a checking list i.e. it doesn't work as an if-else block.

Instead, it indicates when the register/latch specified in the block needs to change states, typically on a clock edge (register) or level change (latch).

If you're trying to detect an edge on an input, such as for an interrupt detection, the recommended way is to synchronise the edge to an internal shift register.

It could be as simple as this:

reg [1:0] det_edge;
wire sig_edge;
assign sig_edge = (det_edge == 2'b10);
always @(posedge clk)
  begin
    det_edge <= {det_edge[0], input};
  end

Then, you can do whatever you want with the edge signal, possibly as an enable signal to a state machine or other block that does something with your device (such as flagging the interrupt).

So, for your application, you may want to do the above twice and then use the two edge detect signals to control some other device/block.

The key point to remember with all HDL work is that HDL stands for Hardware Description Language. It is a replacement for schematics, not software.

For starters, I would recommend starting with the hardware and then translate that into code i.e. draw the schematic and then write the HDL that describes that circuit schematic.

Best Answer

Related Solutions

Electronic – Beginner with fpga and timing issues

Electronic – Verilog: Check for two negedges in always block

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