Electronic – Will a star-shaped Vdd net reduce ground oscillations

emissionsgroundground-planegroundingpcb-design

One of EE.SEs famous answers advocates to use local ground-planes or -nets on ICs that generate broadband noise on power rails (like microcontrollers) in order to reduce excitation of planes as patch antennas and to improve EMI properties. I know there is some controversy about splitting planes, but I would like to ask about a special aspect:

Is using a star layout in the supply-layer (Vdd-star with a ground pour around it) and leaving the adjacent ground-plane unbroken also effective in reducing excitation of ground? Will the placement of such a star point (on center or near border of plane) make a difference?

The thinking behind this: high frequency return currents will be confined to the area below the star and partially cancel each other. Each branch of the star (to be precise: its return current on GND) will excite the plane in a different mode, depending on length and orientation of the branch. I prefer this approach, because this way, signal traces (which have their own return currents) do not have to cross plane boundaries.

I know I can get quantitative answers on such questions for specific cases from FEM analysis, but, not having access to such a tool, I am more after a general rule of thumb.

(Because I reference another post by Olin Lathrop, it may become confusing what "original post" means. Please make clear what you are referring to).

Best Answer

I don't see any flaw in that post's logic. High frequency return currents will be confined to the area below the star point (the post refers to it as a local plane). I can't say anything about EMI cancelling each other but the reduced antenna length will definitely reduce it's gain.

That said, the author of that post repeatedly ignores the dangers of high speed design with this topology. By definition, if all the high frequency elements are isolated to the MCU, your high speed signals leaving the MCU will have terrible slew rates and likely fail eye diagram requirements. He admits that only close to DC signals will leave the plane.

As someone commented, there is no free lunch. There should be a an overall warning that this is only suitable for low speed. Simply put, if any of your communication signals require impedance control, avoid this topology.