I'm new to this concept and parts of it are a little confusing. I understood the part when a 5V signal is applied as input, a channel is formed in the NMOS device, as the positive voltage attracts electrons, thus output is connected to the ground via the NMOS and hence 0 output. But when 0 volts is applies to the gates of both the devices how does the PMOS conduct for the output to be high? Since both are enhancement mode devices a channel does not exist beforehand and is brought about by introduction of a gate voltage. When 0 gate voltage is applied how does a conducting path get formed in the PMOS for the output to connect to VDD?
Electronic – Working of a CMOS inverter
cmos
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Best Answer
Remember that the gate voltage of the PMOS device is relative to its source terminal, which is connected to the VDD supply. So, when the input to the circuit is at 0V, there is a gate bias on that device of –VDD; this is what turns it on and pulls the output high.