Electronic – Yields in DRAM and other Massively Redundant Processes

Here is a (slightly dated) paper that discusses the differences: http://www.ece.neu.edu/faculty/ybk/publication/ASSESSING_MERDRAM_ELSEVIER.pdf

Basically, it boils down to a few important differences.

1. Leakage current. The pass transistors for the DRAM cells must be extremely low leakage, otherwise the leakage current will affect the bit stored in the cell so quickly that data will be lost between refresh cycles. One technique used is substrate bias - the 'bulk' of the wafer is held at a nonzero voltage to change the transistor performance. For logic, you want the substrate sitting at 0V for the best performance (highest speed). The paper indicates that building a DRAM on a 0.5 um logic process would result in a refresh cycle 20 times more often than would be necessary for a DRAM process. The higher refresh rate will cause increased power consumption and can cause delays with memory access.

2. Threshold voltages. High threshold voltages are required to lower the leakage current. However, high threshold voltage transistors are slower to switch as the input voltage has to rise up higher before the transistor will switch, requiring more time. The threshold voltage can be adjusted by applying a substrate bias or by increasing the dopant concentration. The paper states that DRAM process threshold voltages are about 40% higher than logic process threshold voltages. It is possible to dope different transistors different amounts, but this increases the process complexity.

3. On-chip interconnections. DRAM designs are very regular and involve lots of parallel wires with relatively little crossing over. Logic designs require much more complexity. As a result, DRAM processes do not support as many metal layers as logic processes. The surface of a DRAM is also very bumpy due to the construction of the DRAM cells, limiting the number of metal layers that can be used. Logic designs are much flatter and planarization techniques are used (very fine polishing) to flatten (planarize) each layer before the next layer is built on top. DRAM processes generally support around 4 metal layers while logic processes support upwards of 7 or 8. Current logic state of the art is 13 - 14 metal layers.

4. Other issues. DRAM cell leakage must be kept very low to keep the charge in the cell capacitors. The capacitors must also be very area efficient, which is not easy to do with capacitors on silicon. DRAM processes use a rather specialized process to build the capacitors that is not available on regular logic processes.

TL;DR: DRAM processes produce slow logic, logic processes produce leaky DRAM. The main process differences are metal layer count, transistor doping, capacitor construction, and substrate biasing.

Not usually. To read 8 bits, normal practice is to read one bit from each of 8 separate DRAMs.

However, if you were forced by cost or power considerations to use a single device, DRAMs of that era provided both burst mode and page mode, which allow you to provide the column number of the first bit you need, then automatically access adjacent bits in succeeding cycles - in page mode, up to all 256 bits in the currently open row.

(64k DRAMs are well over 25 years old! Where exactly is this question being dug up from - is this an archaeology question?)

The details of page and burst modes differ, and when L1/L2 caches became universal, burst modes evolved to address entire cache lines, wrapping the column address round by modular arithmetic rather than strictly ascending.

Page mode also allowed convenient shortcuts to designers of video cards of that timeframe (25 to maybe 15 years ago).

However, in newer DRAM designs, (the first DDR generation) page mode has quietly been dropped, leaving burst modes so you may have to address every eighth column individually at precisely the right time if you need larger groups of adjacent locations. This makes life more difficult if you're using DRAM without a cache/CPU combination, for example in FPGA applications.