Enhanced 16F PIC: How many instruction periods does automatic_context_save require

interruptspic16f

I am about to do my first design with an enhanced 16F PIC microcontroller. I have a question regarding automatic context save & restore that occurs when an Interrupt is triggered.

Specifically, how many instruction periods does an enhanced PIC16F microcontroller such as the PIC16F1782 require to perform the automatic context save when an interrupt is triggered?

Older 16F PICs without automatic context save require 2 instruction periods to jump to the Interrupt vector and an additional 2 instruction periods to return from Interrupt. Context save within the ISR requires a minimum of 3 instruction periods to save W & Status and context restore when exiting the ISR requires a minimum of 4 instruction periods to restore Status & W.

The datasheet for an enhanced 16F PIC (PIC16F1782) says that all of the following registers are automatically saved in shadow registers when the Interrupt is triggered and restored when the Interrupt Return is executed:
• W register
• STATUS register (except for !TO and !PD)
• BSR register
• FSR registers
• PCLATH register

However, the datasheet doesn't state how much extra time (if any) is consumed by this context save and restore. The closest thing I can find is in the Instruction Set Summary (Table 29-3 on page 344 of the PIC16F1782 datasheet – DS40001579E) which states that RETFIE requires 2 instruction periods (same as the older 16F PICs)..

I have learned the hard way that sometimes the Microchip data sheet isn't always complete.

Best Answer

The information I was looking for is in the datasheet - just not quite where I expected it.

Section 8.2 of the PIC16F1782 datasheet (page 75 of document DS40001579E) states:

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 8-2 and Figure 8.3 for more details.

This information allows me to determine the maximum time that will elapse before my ISR is executed.

Related Topic