Equal rise time and fall time in CMOS circuits

Model level 3 definition: "Semi-empirical" - a more qualitative model that uses observed operation to define its equations. This dates from 1980 ... Any sort of decent result (i.e. within 10% of reality) would need to use level 5 models (AKA BSIM3). I'd recommend using BSIM 3V3 which is model level 49 in Star-HSPice parlance.

As long as you going to be using out of date models then you should heed your prof and only look at the trends. I suspect that there probably is a reason he said that.

You're dealing with curve fitted results.

Additionally, unless you have parasitic extraction enabled the rail capacitances as you noted are almost certainly not being extracted. The CJSW means Capacitance, Junction Side Wall and is a computed values based upon the width and S/D sizes (as one example). There are excellent SPICE guides that tell you what all the parameters are, I suggest you find and read them.

As a general guideline you will want to have the PMOS ~ 2.5X the width of the NMOS (assuming that the lengths are the same). This is because of the mobility differences.

However, I see you are in a smaller process and a node in which some processes implement mobility enhancement in the PMOS, principally through stress. So the guideline may or may not be useful.

Your best bet is to just keep the NMOS at a fixed width and vary the width of the PMOS only. You can also look into the spice file for the process and get the mobility values directly from there.