FPGA floating pins, when place pull-up/down resistor on Input or Output

fpgapulldownpullup

I've looked my FPGA datasheet and found that there is no pull-up/down resistors on it's pins(just a pull-up but that need to be enabled). So, when I power up my circuit I've for a "big" amount of time all IO pins of my FPGA floating. Since I've found that floating IO may damage some device or create problems, I want to put some pullup/down resistors.

Can someone advance me if it's better a pullup or pulldown resistor with which value? I've found someone advice pullup but they in some case can slow signal, other advice pull down, same for resistor values.

My main questions is:
Floating pins can create problems only on input pin of a device or also in output pins?(where input or output are always defined in the device)

Best Answer

This answer was given by a member of Xilinx staff to the same question on the Xilinx forums:

In http://www.xilinx.com/support/documentation/user_guides/ug191.pdf, apge 18, the HSWAPEN pin if pulled to ground, will enable the weak pullups on all IO pins prior to configuration.

After configuration, a pin may be set to pull up, or pull down, or to remain floating (effectively tri-state) or be driven high or driven low, depending on the IO standard chosen. It does no harm to have pins float.

The default in the software is probably not something you would like to rely on. It is far better to design the IO to do what you want it to do and state it explicitly.

I believe the default is a weak pull down for unused pins, however.

The weak pull up and weak pull down may often be too weak: a resistor of the proper value is recommended if there is a standard that you are trying to meet, as opposed to relying on the weak internal pull up or down.

Austin
Austin Lesea
Principal Engineer
Xilinx San Jose

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