Refer to this question I had asked a few days back:
PWM DAC Filter explanation
Hi, It is getting extremely difficult for me to create the PT0 and PT1 signals as given above. I am using a dsPIC30F device. Two PWMs are created with independent duty cycle control, however, the duty cycle change happens by controlling falling edge, where as the above demands that PT0 must have fixed falling edge and variable rising edge…how to achieve that?
On the other hand, I am thinking of using a simple 4th order sallen-key LPF to filter out most of the PWM fundamental…and set its cut-off to say less than half of the PWM fundamental. My sampling frequency for the DAC output (yes, I am sampling my own DAC output) is LOW about once in every 25ms.
Can I remove the left over ripple, by using a small LC filter in line with the DAC output…this works in voltage regulators…will it work here. The output is going to drive a high input impedance OpAmp…so current drive capacity is not in question.
Any pointers?
Best Answer
From your previous question, it sounds like Dave does not recommend using that method.
There likely isn't a point in using an LC filter in line after the 4th order sallen-key. Depending on the quality of your sallen-key, you may not get any more benefit out of an LC filter.
With such a low sampling frequency, and no need for high output impedance, why aren't you maximizing the PWM frequency and filtering it with an appropriate RC filter?
From your datasheet: "PWM Frequency for 11-bit resolution (@ 30 MIPS) = 29.3 KHz for Edge-Aligned mode"
Your sample frequency is 40 hz which is 3 orders of magnitude different. A single RC filter gives you a single order filter which gives 20db/Dec. With 3 decades of drop-off, you should get a pretty smooth signal out relative to your sample rate.