High side switch using complementary MOSFET: pull up/down calculation

mosfet

For a battery powered ultra low consumption application I designed a classical high side switch using the complementary MOSFET FDMA1032CZ. this is the schematic:

enter image description here

The idea is simple:

  • before shipping, the circuit consumption is nearly 0[A] (only MOSFET and battery leaks),
  • then the user powers on the circuit using switch S1,
  • the microcontroller starts running and activates Q1-N and Q1-P via "PWR_ON" signal,
  • the circuit is then continuously powered on by the battery through the mosfet switch.

I need assistance to calculate the optimal value for both pull-up and pull-down resistors (R1 and R2). For reminder, those 2 resistors are mandatory to set voltage level when circuit is powered on.

In my opinion those resistors must be :

  1. as large as possible to minimize current when the 2 mosfets are on,
  2. but not too big to make sure the 2 mosfets can switch fully on.

When looking at datasheet, it appears that the maximum MOSFET gate body leakage IGSS_max = +/-10[uA] and the minimum gate threshold voltage VGSth_min = +/-0.6[V].

According to previous point 2), the resistor value should NOT be greater than R_max = VGSth_min/IGSS_max = 0.6/10e-6 = 60[kohm].

For a battery voltage of 3V, this would result in a total consumption through the resistors of: I = 2x V_BAT/R = 2x 3/60e3 = 100[uA], which is far too big…

I would appreciate if someone could confirm and/or correct my calculation.

Best Answer

It seems your calculations are correct.

This IGSS is untypically high for mosfets. I think this is because of zener diodes on gate. Typical value is ±100 nA.

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