I need some input on implementation of a high-speed (>100Mbps) wireless digital communication design.
The part which concerns me is from the data input to the RF PA, we got a guy working one the project, who is an analog RF expert, so he can build the PA.
I was thinking about something like this (shown for the TX):
data -> FPGA -> DAC -> I/Q Modulator -> PA -> ANT
But are there some standard available chipset for doing this?
Or some document describing an example design?
And is I/Q modulation a good way to go?
Best Answer
(Stream of consciousness notes and comments)
Well, I/Q is the way to go. Is this 100M Bits or Bytes/Second? There's a big difference. @ 100MBit/Sec you might be able to use an wifi approach. I don't think wifi will support 100MByte/Sec.
If you have to roll your own system, then you'll need to worry about framing, error correction, synchronization, filtering, etc.
Is this intended to be a full duplex system? in other words, do you need to transmit from both sides of the communications link?
You'll need a fair amount of modulation bandwidth, probably 50 MHz or more, so what frequency band are you planning on using, and how far does this need to go. There's been a lot of work in the 60GHz band recently for short distance, and there's plenty of data bandwidth there, that might be something to think about.