The task is to generate a CMOS (+-5[V]) square wave signal with 50% duty cycle in order to drive a second order active filter IC (MF5CN) with variable or fixed frequencies of 150[Khz], 300[kHz], 750[kHz] and 850[kHz].
This clock is to be powered from a signle power supply.
THe problem is that the more "clean" (accurate) the square signal is, the better the performance of the filter (more accurate at the cut-off frequency)
I've already tried the HEX inverter using the HD74HC14 circuits but at the listed rate of frequencies there is a lot of distortion, so ¿How can I reduce or to "clean" this signal in order to make it as much accurate as I can?
The DDS aproach would be an option but it would be way too much of an overkill, and in fact a much more complicated project than the one I am trying to accomplish now.
As soon as I can post a picture I'll upload the screenshot of the scope.
Other methods to generate the said signal are also welcome as long as it is the more cheap and it does use the less components.
Best Answer
To eliminate the distortion of the duty cycle you want to generate your frequency at twice the desired value and then divide it by two using a D type FF (flip flop). Use a part such as a 74HC74 type. Connect your 2x frequency to the CLK pin of the flip flop. Then connect the D input pin to the inverted Q output. Take the Q output as the 1x frequency with very nice 50% duty cycle. The PRE and CLR inputs of the flip flop need to be pulled up to the positive supply rail via a resistor such as 10K ohms. Also remember to add a 0.1uF bypass capacitor between the V+ and GND pins at the chip.