This is with reference to the question asked here: Finding Critical Path of Combinational Logic. When design compiler command report_timing is run, it appears the timing requirement for the combinational multiplier doesn't get reported (I say this because I expect the multiplication to be the critical path). Will the circuit still be able to run at the given frequency even though it appears that the timing requirement for the multiplier circuit was ignored? From the answer in the link provided, I understand report_timing only reports timing for register-register paths, in general, should registers be applied to all combinational paths in a digital circuit in order to get a correct functionality/ timing report?
How does design compiler constrain combinational paths
digital-logicverilog
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Best Answer
Generally the timing analysis is done register-to-register. The analysis should check all possible paths - it doesn't try to figure out which one is critical, it just calculates all of them and then sorts the list by the path length. It is possible to have timing constraints against I/O pins which are not registered, but this is more of a special case. The timing requirement should not be getting ignored unless there is an issue with how the software determines the paths. It is possible, for example, for the critical path you're interested in to get optimized away. Also, note that the timing of a particular block will vary depending on how it is placed. You could get different performance when you place the block by itself vs. as a component of a larger design.