How should this code look like in verilog

computer-architecturedigital-logicintegrated-circuitsystem-verilogverilog

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me that its not verilog, but I thought I saw a youtube video with verilog if statements like that. If this code is not verilog, then how should its verilog counterpart that implements the same functionality look like?

sorry, i can't find a clear picture, the website i upload pictures blurred this one for some reason. I also can't copy paste because right now i can't connect to my school's server to access the programs.

Best Answer

That code is not verilog. It looks like it is probably C. However, it is possible to use an if statement in verilog. Looks like the only thing you need to do to make that code into valid verilog is to replace the { and } with begin and end. However, you may need to put it inside an always block of some sort for it to work correctly.

Related Solutions

How the below verilog code run when it find positive edge of clock

In this case, the execution order should be as follows (in this exact order):

Time X:    if-statement
Time X+5:  case
Time X+5:  Statement 1
Time X+10: Statement 2

What you are running into is confusion about blocking vs non-blocking assignment. This is a nice example as to why it is called non-blocking assignment. When you hit the line #5 window[i]<=douta;, the simulator will wait 5 time units, then schedule window[i] to take on the value of douta at the end of the current time step. Because you used the non-blocking assignment operator, the execution of the always block continues to the next statements, which is the case statement. Since the assigns here are blocking assignments, they are executed immediately. Then, the #5 is hit (after the case), so the scheduler schedules the next execution for 5 time units in the future. Then it moves on to anything else it needs to do. Finally, it comes back (still within time step X+5) and completes all the non-blocking assignments (like window[i]<=douta). Thats why you are seeing what looks like non-inorder execution of your always block.

Electronic – How to remove this warning in Verilog

If you know that you don't need the signals, ignore the warning. But why would you declare a 9 bit bus whilst only needing one signal? That's bad practice.

Generally about such warning:

You should definitely worry about it!

This warning means that you're not using signals that you've declared so synthesis -- being the clever thing that it is -- optimised those away. This usually suggests that there's something logically wrong in your implementation and that your output will not be what you intend it to be.

Only ignore warnings that you fully understand.

Finally, don't switch off that warning type as you will not see it when it actually matters!

Best Answer

Related Solutions

How the below verilog code run when it find positive edge of clock

Electronic – How to remove this warning in Verilog

Related Topic