# How to calculate cache size

assemblycachecpumicroprocessor

A cache with a line size of L 32-bit words, S number of sets, W ways, and
addresses are made up of A bits. Assume that the cache is word addressed, i.e., the low two bits of the address are always 0.

1. If this is a direct-mapped cache of size 16 words, line size 4 words, what is the cache size in bytes? This number should include just the data portion of the cache

2. What is the total number of bytes required to store the tags?

This problem is very abstract for me, so helpful hints on calculating the cache size and tags would be apreciated.

If the words are 32 bits, and there are a total of 16 words, does that mean the cache size is 16 * 32 = 512 bits = 64 bytes (Question 1)? This would also be important to answer 2) the number of bytes required to store the tags.

1) If the cache is direct-mapped (i.e. 1 way) of 16 words, its size (excluding tags) is 16*4=64 bytes. Line length does not matter.

2) There is a mismatch between "A address bits" and "tag size in Bytes"

Each tag contains :

• A validity bit

• The portion of addresses not indexed in the cache.

• Usually some history bits for the various cache replacement algorithms (LRU, PLRU), used on multiways caches.

Each cache way size is (in bytes) : 4(bytes per word)*L(line size)*S(sets)

• From the A address bits , you must place (A-ln2(L)-ln2(S)-2) address bits in the tags.
• There is 1 tag per cache line. So there is W(ways) * S(sets) tags in your cache.

Even if question 2) is about the cache described in question 1), you cannot answer without knowing the number of address bits.