How to Design Binary Multiplier for 2 bits

What's considered the maximum number of parts on a single page?

Depends on the size of the page. You can fit more on a D-sized plotter sheet than a B-sized (roughly A4) sheet. Don't crowd things to the point it gets difficult to read.

What to consider when making a schematic multiple pages?

Almost all my designs end up as multiple sheets. Sometimes the manufacturing guys cut them all up and paste them together in one big plotter sheet to make it easier to follow the signal flow. But normally I don't print out bigger than 11x17 so I work at that size.

Something you didn't ask: I tend to make the first sheet be the critical input and output connections of my circuit, and work up towards more complex circuits on later pages. Other people like to put the critical signal path parts on the first page, and the input and output connections end up deep in the stack of schematics. I'm not sure which is really better.

When should I consider putting multiple tracks into a buss?

I rarely do this, but its a matter of style (and convention in your workgroup).

How should I name busses, netlists, and the references to other pages?

I tend toward all-caps net names, but otherwise I don't have fixed rules. More disciplined organizations might have more detailed rules.

How should I place components to minimize the number of nets?

I prefer to place components to make the signal flow clear. I don't worry about the number of named nets.

What kind of comments should I include on a schematic?

Anything important for the layout guy to know (matched length traces, place bypass caps near ICs, etc.) Anything a future engineer might need to know if they're looking to replace an obsolete part. Non-obvious critical specs like higher-than-normal resistor power requirements or tight tolerances. Anything that has to be tuned in production (Like "tune pot to achieve 50% duty cycle" or whatever).

Where should I place the designation and value for horizontal and vertical components? Does it matter as long as I stay consistent?

I use vertical text for vertical components to allow more parts to fit cleanly on a sheet. Others (apparently) consider this a grave sin. Be consistent and be consistent with others in your organization.

Should I note component packaging & rating on the schematic? Meaning discrete vs SMD or if a specific resistor is high powered?

Specifying the package type for each part visibly on the schematic would be clutter. But obviously that information has to be in the design to get transferred to layout. As mentioned above mention nonobvious specs that might trip someone up if they have to replace an obsolete part or find an alternate vendor due to a shortage.

Your BOM (Bill of Materials) will need to specify an exact manufacturers part number (or a list of acceptable alternates called an AVL "approved vendor list") for each part.

Should I customize nets in different colors or widths?

I don't recommend this. I'd prefer to get schematics that make sense if printed out in black & white.

How should I version control schematics?

I store datecoded backups (like "mydesign_20120205.zip" on my own pc and a remote share drive. Definitely store a backup whenever you release a design (either to layout or to manufacturing).

Edit: There are better ways to do this (see comments) but a simple process like dated zip files is also perfectly workable.

What workflow should a single person use to keep designs organized?

Keep backups. Use all the tools you have available. If you aren't doing your own layout, keep good communication with the layout guy.

There are a number of architectures, actually. And they're not as different as claimed by the different vendors (although there are still differences.)

NVIDIA typically builds GPUs that work a lot like general-purpose CPUs: There's a large framebuffer out in GDRAM, there's a number of large caches for texture fetch and buffering, and there are groups of pixel processors (typically 4x2 pixels) that operate on some particular primitive at a time. For framebuffer blending or writing, the I/O goes through the memory bus, somewhat helped by the caches. If multiple different objects cover the same pixels (overdraw) then the same pixels may go to/from the framebuffer more than once during a particular frame.

POWERVR and Intel typically build "tiled" processors, where they have a similar architecture (4x4 tiles IIRC) but to avoid the big input/output load on the GDDR, they sort all the primitives ahead of rasterization, so they only need to load/write a particular block of framebuffer pixels once per frame. At least, that's their design goal -- this is not always necessarily achieved. The benefit is that you need to spend less bandwidth on reading and writing back framebuffer pixels. However, approximately the same amount of texture bandwidth is used, so the savings aren't necessarily orders of magnitude (it's scene dependent.)

The Xbox architecture is a bit of a hybrid -- it has EDRAM that's bigger than itty-bitty tiles, but smaller than a full HD framebuffer. The GPU runs through the primitives, and writes them to the EDRAM, which then "resolves" to the output framebuffer (this also calculates things like anti-aliasing.) The EDRAM framebuffer is made to be effectively fast enough to be non-blocking. The screen will be split into some number of tile areas -- 1 through 4 for a particular frame, typically.