How to determine if the clock signal suffers from high speed effects

high speedsignal integrity

I need to determine if the clock signal inside a multichip module shall suffer from high speed effects i.e reflection and ringing. I have:

(1) IBIS models of the components inside the multi-chip module

(2) The IBIS models in (1) converted to PSpice Models

(3) length of PCB tracks of the clock signals and the propagation delay on them and their characteristic impedance

(4) Cadence Design suite with the following software:

Allegro PCB Planner
Design Entry CIS
Design Entry HDL Rules Checker
Design Entry HDL
FPGA System Planner
Library Explorer
License Client Configuration Utility
OrCAD Capture CIS
OrCAD Capture LITE
OrCAD Capture View-Only
OrCAD Capture
Package Designer
PCB Editor
PCB Route
PCB SI
Physical Viewer
Project Manager
PSpice AD
PSpice Advanced Analysis
SiP Digital Architect
SiP
System Architect

There are also some more directories

AMS Simulator
PCB Editor Utilities
PCB SI Utilities
PSpice Accessories

What do I do next to carry out this signal integrity simulation? If the clock signal starts from the oscillator and then after a few milimeters, splits into multiple tracks which connect to different components, does that cause impedance discontinuity and thus high speed effects?

Best Answer

The tool you are looking for is called SigXplorer. Since you have the PCB SI license, I suspect it's part of your package. Try Start>Run and then type SigXplorer.

It will allow you to do things like this:

enter image description here

Your colors will be different, but you get the idea. Let me know if you need help with this.

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