I want to use a JK flip flop in order to create a toggle output. It is clear that both J and K should be set to 1, as well as the Preset and Clear inputs.
In some schematics, a Monostable 555 followed by a NOT gate, appears to connect with the Clear.
I think that the Mono creates a pulse and after that it stops, so connected with a NOT gate, the output of the NOT gate should create a power "gap" and after that it should continue powering the Clear input.
It looks like a delay in inserted, in order to power up first the Preset input and second the Clear input.
If that is the case, it's OK, even though I can't understand the reason for that. Yet, I have created a simple toggle circuit without a time delay, thus both Preset and Clear are power simultaneously, and it seems to work fine.
Actually, I have created two circuit versions, with one and two flip flops, meaning one and two outputs, and both work fine.
Do I miss something there? The same question goes with the T flip flop as well.
Thank you.
Best Answer
For a typical flip-flop, you only need a few ns of delay after power-up to set the logic. If the input to the flip-flop has a Schmitt trigger design, you can use a simple R-C divider across the rails. Connect the reset line to the center of the divider. If you need a high value for reset and a low for operation, connect the resistor to ground and the cap to +Vcc. It's the reverse for opposite logic.
The way it works is that for the power-on transient, the capacitor behaves as a short circuit and the voltage across the cap will be near-zero for a while after power comes on. Then, as the cap charges, the voltage as the midpoint moves (slowly) to the other rail. This slow RC behaviour is why you need Schmitt inputs on the signal.
If you need fast reset for power cycling, you can put a reverse-biased diode across the cap to encourage fast discharge when power is removed.