How to toggle a reset in a counter made up of JK flip flops

I think the things that is really missing from your design are signals, signals exist inside the architecture and can be assigned in much the same way as a port but without an interface to the outside world, a signal can be written to and read from and can be any type you like and an output can be assigned a signal of the same type so for your design consider using an internal register and then assigning it to your output.

Here's an example of what I mean:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;

entity lfsr is

    port (

        -- Clocks
        clkin                                   :in  STD_LOGIC; 

        -- Initialisation data
        first_key                               :in  STD_LOGIC_VECTOR(3 downto 0);

        -- Control Signals
        key_set                                 :in  STD_LOGIC;
        push                                    :in  STD_LOGIC;

        -- Outputs
        data_out                                :out STD_LOGIC_VECTOR(3 downto 0);              
        );

end lfsr;   

architecture RTL1 of lfsr is    

    signal key                      :STD_LOGIC_VECTOR(3 downto 0);

begin                                                                                                               

    -- Generate a key every time the push signal is asserted
    process(clkin)
    begin

        if rising_edge(clkin) then

            if key_set = '1' then -- Initialises the key

                key <=  first_key; 

            elsif push = '1' then -- Generate a new key

                key(2 downto 0) <=  key(3 downto 1);
                key(3)          <=  key(1) XOR key(0);

            end if;

        end if;

    end process;

    -- Send internal key to output port
    data_out    <=  key;

end RTL1;

so the signal that I have created is key, it is internal to the architecture and what it actually represents is a block of memory 4 bits wide. This code actually does what you want, it is a LFSR that will generate pseudo random data but I have made it 4 bits wide instead of 8 because I didn't want to just give you the answer and if you can understand what this code does, you will be able to understand how to expand it to 8-bits and it will be a great start to understanding VHDL.

If you have any questions about my code then please ask,

Gipsy

"What does it mean when a flip flop performs a function like SET, CLEAR, HOLD, or TOGGLE?"

first I'll like you to explain about latches.There is not much difference between latches and flipflop.Latches don't have clock input but flipflop have clock inputs.Here is a simple Set-Reset latch
.
Explanation for SET:From the name,it suggests that,when you apply Logic HIGH to 'S'(Set),this sets the output Q to logic HIGH.The not(Q) will be it complement(logic LOW)
.
Explanation for RESET:If you apply logic HIGH to 'R'(Reset),it makes the output Q to logic LOW,then not(Q) will be HIGH.(note that 'S' should be in logic LOW at that time).
Explanation for HOLD:If you apply Logic LOW to both input(S and R),The output doesn't change.I mean,it HOLDS the past output.
Explanation for TOGGLE:If you apply both pins with logic HIGH,it leads to indeterminate state for SR latch and it's the limitation of SR latch,so if you consider J-K flipflop,when you apply both J and K with Logic HIGH,it changes the output(ie. output HIGH goes to LOW and vice versa).This is called as TOGGLING.

"I start with a clock signal that goes into each flip flop. From there, I really have no clue how to trace what's going on."

Please note that,clock signal is to activate the latch circuit.A Latch with Clock pulse is called as Flipflop.Applying clock signal to activate a latch is called as Triggering.There are two types of triggering.One is edge triggering and the other is level triggering.

.In level triggering,The flipflop is ready to get the input throughout the Level of the clock continuous.In edge triggering,The flipflop will be ready to get input only when the edge of the clock is detected.Always edge triggering is preferred.